Method and structures for indexing dice

• US 7,348,682 B2
• Filed: 04/19/2005
• Issued: 03/25/2008
• Est. Priority Date: 04/19/2004
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Valtolina, Marco Natale, Brambilla, Daniele Alfredo
• Primary Examiner(s): Potter; Roy Karl
• Application Number:
  US11/109,977
• Publication Number:
  US 20050275068A1
• Time in Patent Office: 1,071 Days
• Field of Search: 257/797, 257/758, 438/401
• US Class Current: 257/797
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54466 Located in a dummy or reference die
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer.

Claims

1. A die obtained from a material wafer comprising a plurality of stacked material layers, the die being provided with a visible index indicative of a respective die position of the die in the wafer, the visible index includes

a reference structure formed in a first material layer of the die and adapted to defining a mapping of the wafer;

and

a marker formed in a second material layer of the die, associated with the reference structure, and adapted to providing an indication of the respective die position.

2. The die according to claim 1, obtained from a semiconductor material wafer, wherein the die includes integrated circuits formed in the plurality of stacked material layers.

3. The die according to claim 1, wherein the first material layer of the die coincides with the second material layer of the die and particularly includes one among a metal layer, a polysilicon layer, and a passivation layer.

4. A die obtained from a wafer, the die comprising:

first and second layers;

a first reference disposed in the first layer and defining first points that each represent a respective region of the wafer; and

a first marker disposed in the second layer and in alignment with the first point that corresponds to the region of the wafer in which the die was located.

5. The die of claim 4 wherein the first and second layers comprise the same layer.

6. The die of claim 4, further comprising:

wherein each region of the wafer included multiple dies;

third and fourth layers;

a second reference disposed in the third layer and defining second points that each represent a respective position within each region of the wafer; and

a second marker disposed in the fourth layer and in alignment with the second point that corresponds to the position of the die within the region of the wafer in which the die was located.

7. The die of claim 6 wherein the first layer, second, third, and fourth layers comprise the same layer.

8. The die of claim 4, further comprising circuitry.

9. The die of claim 4, further comprising:

wherein each region of the wafer included multiple dies;

third and fourth layers;

a second reference disposed in the third layer and defining pairs of second points, each pair of second points representing a respective position within each region of the wafer; and

second and third markers disposed in the fourth layer and respectively in alignment with the second points of the pair that corresponds to the position of the die within the region of the wafer in which the die was located.

10. The die of claim 4 wherein the first reference defines a two-dimensional array of the first points.

11. A wafer, comprising:

a plurality of dies each comprising,

first and second layers,

a reference disposed in the first layer and defining points that each represent a respective region of the wafer, and

a marker disposed in the second layer and in alignment with the point that corresponds to the region of the wafer in which the die is located.

12. An integrated circuit, comprising:

a package; and

a die obtained from a wafer, disposed within the package, and comprising,

first and second layers,

a reference disposed in the first layer and defining points that each represent a respective region of the wafer, and

a marker disposed in the second layer and in alignment with the point that corresponds to the region of the wafer in which the die was located.

13. An electronic system, comprising:

integrated circuit, comprising,

a package; and

a die obtained from a wafer, disposed within the package, and comprising,

first and second layers,

a reference disposed in the first layer and defining points that each represent a respective region of the wafer, and

a marker disposed in the second layer and in alignment with the point that corresponds to the region of the wafer in which the die was located.