Low leakage and data retention circuitry

• US 7,348,804 B2
• Filed: 04/02/2007
• Issued: 03/25/2008
• Est. Priority Date: 02/19/2004
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosid Delaware, Inc.
• Inventors: Cole, Andrew, Callahan, John M., Walker, William G., Zampaglione, Michael A., Hoberman, Barry A., Hillman, Daniel L.
• Primary Examiner(s): LE, DON P
• Application Number:
  US11/732,181
• Publication Number:
  US 20070176639A1
• Time in Patent Office: 358 Days
• Field of Search: 326/37, 326/38, 326 82- 86, 326/104, 326/46
• US Class Current: 326/82
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/356086 with additional means for controlling the main nodes H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Claims

1. A data retention circuit apparatus, the apparatus comprising:

an input/output pad cell comprising level shifter circuitry with inputs and outputs;

output latching circuitry comprising at least two transistors coupled to the outputs of the level shifter circuitry and configured to retain a state of the level shifter circuitry based on the state of the inputs; and

a leakage optimization circuit configured to decrease leakage power in tandem with the state retention of the output latching circuitry.

2. The data retention circuit apparatus of claim 1, wherein the input/output pad cell is configured to interface with chip core logic.

3. The data retention circuit apparatus of claim 1, wherein the level shifted circuitry inputs are configured to accept a thin gate device during an input stage.

4. The data retention circuit apparatus of claim 1, wherein the level shifter circuitry inputs include at least two depletion-mode transistors.

5. The data retention circuit apparatus of claim 4, wherein the at least two depletion-mode transistors are configured to allow for an increased voltage ratio.

6. The data retention circuit apparatus of claim 1, wherein the gates of the at least two depletion-mode transistors are further coupled to at least two other transistors, the at least two other transistors coupled to a cascode voltage.

7. The data retention circuit apparatus of claim 1, further comprising at least two other transistors, wherein the sources of the at least two other transistors are coupled to a common SLEEPB transistor.

8. The data retention circuit apparatus of claim 7, wherein a data retention state results from the application of logic low to the SLEEPB transistor.

9. The data retention circuit apparatus of claim 1, further comprising an inverter configured to control the inputs of the level shifter circuitry.

10. The data retention circuit apparatus of claim 9, wherein the level shifter circuitry and the inverter both include at least one sleep (SLPB) transistor.

11. The data retention circuit apparatus of claim 10, wherein the level shifter circuitry switches off prior to an output of the inverter drifting to a positive supply voltage.

12. The data retention circuit apparatus of claim 1, wherein the transistors of the output latching circuitry include an n-field effect type transistor (NFET).

13. The data retention circuit apparatus of claim 12, wherein the NFETs include a thick gate oxide.

14. The data retention circuit apparatus of claim 12, wherein the gate of a first NFET of the output latching circuitry is coupled to the drain of a second NFET of the output latching circuitry.

15. The data retention circuit apparatus of claim 14, wherein the gate of the second NFET of the output latching circuitry is coupled to the drain of the first NFET of the output latching circuitry.

16. The data retention circuit apparatus of claim 1, wherein the outputs of the level shifting circuitry are coupled to a static random access memory (SRAM) cell, and the inputs of the level shifting circuitry are configured to be removed subsequent to the output latching circuitry switching to a new state.

17. The data retention circuit apparatus of claim 1, wherein a same logic level on a first input of the level shifter circuitry is output in response to a second logic level on a second input of the level shifter circuitry.

18. The data retention circuit apparatus of claim 1, wherein the at least two transistors coupled to the outputs of the level shifter circuitry are implemented in a cascode voltage switch logic (CVSL) environment.

19. A system for controlling power consumption within an integrated circuit, the system comprising:

a power island including a first circuit, the first circuit configured to;

receive input signals;

receive a hold signal;

process the input signals;

retain data in a sleep state having low leakage; and

retain the data based on the hold signal;

a sleep transistor coupled to the first circuit, the sleep transistor configured to;

receive a negative voltage sleep signal; and

reduce power consumption of the first circuit in the sleep state, wherein the first circuit has low leakage based on the sleep signal while simultaneously retaining the data.

20. The system of claim 19, further comprising a power island manager coupled to the power island, the power island associated with a delineated partition of the integrated circuit.

21. The system of claim 20, wherein the partition of the integrated circuit is geographic.

22. The system of claim 20, wherein the partition of the integrated circuit is functional.

23. The system of claim 20, wherein the power island manager is configured to select a clock signal to control power consumption by the power island.

24. The system of claim 20, wherein the power island manager is configured to modify a voltage within the power island to control power consumption by the power island.

25. The system of claim 20, wherein the first circuit is further configured to deactivate the sleep state in response to a control signal received from the power island manager.

26. The system of claim 23, wherein the power island manager further comprises a register and a data retention state machine, the data retention state machine configured to time writing to the register, wherein writing to the register controls a sleep mode of the power island.

27. The system of claim 26, wherein the frequency of the clock signal sequences writing to the register by the data retention state machine.

28. The system of claim 19, further comprising an adaptive leakage controller configured to regulate a voltage applied to the sleep transistor.

29. The system of claim 28, wherein the sleep transistor is further configured to power up the first circuit based on a power up state indicated by the sleep signal.

30. The system of claim 19, wherein the sleep transistor is an NMOS transistor.

31. The system of claim 19, wherein the sleep transistor is a PMOS transistor.

32. The system of claim 19, further comprising a:

a level shifter circuit including inputs and outputs; and

an output latching circuit comprising at least two transistors coupled to the outputs of the level shifter circuitry and configured to retain a state of the level shifter circuitry based on the inputs.

33. The system of claim 32, further comprising an inverter configured to control the inputs of the level shifter circuitry.