Input buffer

• US 7,348,809 B2
• Filed: 03/23/2006
• Issued: 03/25/2008
• Est. Priority Date: 03/23/2006
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Eldredge, Adam B.
• Primary Examiner(s): Lam; Tuan T.
• Assistant Examiner(s): O'Neill; Patrick
• Application Number:
  US11/387,357
• Publication Number:
  US 20070222484A1
• Time in Patent Office: 733 Days
• Field of Search: 327/65, 327/108, 327/333, 327/560, 327/561, 327/562, 327/563, 327/315, 327/316, 327/318, 327/319, 327/323, 327/324, 327/327, 327/328, 327/379, 327/391, 330/252, 330/253, 326/83
• US Class Current: 327/108
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 2203/45654 the LC comprising one or more extra diodes not belonging to mirrors
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/45722 the LC comprising one or more source followers, as post buffer or driver stages, in cascade in the LC
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45713 Controlling the active amplifying circuit of the differential amplifier
• CPC Class Codes: H03F 3/45744 by offset reduction
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a wide range of levels extending from a low end lower than a supply voltage of the input buffer to a high end exceeding the supply voltage.

Claims

1. An input buffer comprising:

a common gate amplifier having input terminals coupled to receive an incoming common mode voltage, wherein the common gate amplifier is configured to receive the incoming common mode voltage that extends beyond a supply voltage of the input buffer; and

a bias circuit coupled to provide a bias voltage to gate terminals of the common gate amplifier, wherein the bias circuit is configured to provide the bias voltage at a level higher than the supply voltage of the input buffer, the bias circuit having a diode-connected current mirror transistor and a bypass capacitor coupled in parallel therewith and coupled between a resistor pair and the gate terminals of the common gate amplifier.

2. The input buffer of claim 1, wherein the bias circuit is coupled to receive the incoming common mode voltage and to generate the bias voltage therefrom.

3. The input buffer of claim 1, wherein the common gate amplifier comprises a level shifter and a first gain stage coupled to directly receive the incoming common mode voltage from a driver circuit.

4. The input buffer of claim 3, further comprising a second gain stage coupled to output terminals of the first gain stage, the second gain stage configured to receive an output voltage of the first gain stage at a level lower than the supply voltage of the input buffer.

5. The input buffer of claim 4, further comprising a feedback circuit to receive an output voltage of the second gain stage and to control a gate voltage of a pair of input transistors of the first gain stage to introduce hysteresis.

6. The input buffer of claim 4, further comprising a voltage limiting circuit coupled to the output terminals of the first gain stage to limit the output voltage of the first gain stage to less than the supply voltage of the input buffer.

7. The input buffer of claim 4, further comprising a voltage limiter coupled to the output terminals of the first gain stage to limit the output voltage to a predetermined level.

8. The input buffer of claim 1, wherein the common gate amplifier comprises:

a pair of transistors having the gate terminals commonly coupled, the pair of transistors having input terminals coupled to receive the incoming common mode voltage and output terminals coupled to provide an output voltage; and

the bias circuit to bias the gate terminals, wherein the bias circuit is coupled to receive the incoming common mode voltage and to generate the bias voltage therefrom.

9. The input buffer of claim 1, further comprising a current source coupled to the gate terminals of the common gate amplifier, wherein the current source is controlled by a feedback circuit.

10. The input buffer of claim 1, further comprising a pair of diode stacks each having a first plurality of diodes coupled between the supply voltage of the input buffer and one of the input terminals of the common gate amplifier and a second diode coupled between the corresponding input terminal and a ground voltage.

11. The input buffer of claim 10, wherein the pair of diode stacks is to limit a maximum voltage of the incoming common mode voltage.

12. A method comprising:

receiving an input common mode voltage at input terminals of a common gate amplifier of a first gain stage of an input buffer;

directly amplifying and level shifting the input common mode voltage in the first gain stage of the input buffer from a first voltage that extends beyond a supply voltage of the input buffer to a second voltage no larger than the supply voltage;

providing an output of the common gate amplifier to a second gain stage at the second voltage;

providing an output of the second gain stage to a feedback circuit;

controlling a first transistor of the input buffer with a first voltage generated by the feedback circuit; and

controlling a second transistor of the input buffer with a second voltage generated by the feedback circuit, wherein the feedback circuit is gated by a feedback signal from the input buffer.

13. The method of claim 12, further comprising biasing the common gate amplifier using the input common mode voltage.

14. A system comprising:

a driver to transmit differential signals; and

a buffer coupled to the driver, the buffer having a first gain stage coupled to receive the differential signals, wherein the first gain stage is configured to receive the differential signals at a voltage level that exceeds a supply voltage of the buffer, the buffer including a bias circuit to provide a bias voltage to gate terminals of the first gain stage, wherein the bias circuit is coupled to receive the differential signals and generate the bias voltage therefrom, the bias circuit having a diode-connected current mirror transistor and a bypass capacitor coupled in parallel therewith and coupled between a resistor pair and the gate terminals of the first gain stage, and a controllable current source coupled to the gate terminals of the first gain stage, the buffer further including a pair of diode stacks each having a first plurality of diodes coupled between the supply voltage of the buffer and an input terminal of the first gain stage and a second diode coupled between the input terminal and a ground voltage, and a voltage limiter coupled to output terminals of the first gain stage to limit an output voltage of the first gain stage to a predetermined level.

15. The system of claim 14, wherein the first gain stage comprises a common gate amplifier having input terminals coupled to receive the differential signals, wherein the differential signals are substantially greater than the supply voltage of the buffer.

16. The system of claim 14, further comprising:

a physical media attach (PMA) device comprising a framer including the driver; and

a physical media dependent (PMD) device comprising a serializer/deserializer including the buffer.

17. The system of claim 14, further comprising:

a first integrated circuit (IC) coupled to a motherboard and to receive a first supply voltage therefrom, the first IC including the driver; and

a second IC including the buffer coupled to the motherboard and to receive the supply voltage of the buffer therefrom, wherein the first supply voltage is greater than the supply voltage of the buffer.

18. The system of claim 17, wherein the differential signals comprises low voltage positive emitter coupled logic (LVPECL) signals, and the buffer is to convert the LVPECL signals to low voltage differential signals.

19. An apparatus comprising:

means for receiving an input common mode voltage in an input buffer;

gain stage means for directly amplifying and level shifting the input common mode voltage from a first voltage that extends beyond a supply voltage of the input buffer to a second voltage no larger than the supply voltage; and

feedback means coupled to the gain stage means and between a bias voltage node of the gain stage means and a current source, the feedback means for receiving an output of a second gain stage means and independently controlling a first gate terminal and a second gate terminal of the gain stage means based on the output.

20. The apparatus of claim 19, wherein the means for receiving comprises input terminals of an amplifier of the gain stage means.

21. The apparatus of claim 20, further comprising means for biasing the amplifier using the input common mode voltage.