Sparse refresh of display

• US 7,348,987 B2
• Filed: 11/14/2005
• Issued: 03/25/2008
• Est. Priority Date: 12/07/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Willis, Thomas E., Midford, Steven L.
• Primary Examiner(s): Chauhan; Ulka
• Assistant Examiner(s): WASHBURN, DANIEL C
• Application Number:
  US11/273,001
• Publication Number:
  US 20060061581A1
• Time in Patent Office: 862 Days
• Field of Search: 345/545, 345/531, 345/544
• US Class Current: 345/545
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A method, apparatus, and signal-bearing medium for sending to a display device modified regions of a frame buffer. A frame buffer is divided into the regions, and data in the frame buffer represents pixels on the display device. The frame buffer accumulates writes until the region being written to changes, at which time the region is copied to the display device.

Claims

1. A method, comprising:

representing a frame buffer as a plurality of regions, each region having a plurality of pixels that span multiple different rows within each region, and wherein each region has a configurable shape;

accumulating writes to a first region of the plurality of regions within the frame buffer;

detecting a new write to a different region from that of the first region; and

asynchronously writing the first region to a display device upon detection of the new write.

2. The method of claim 1, wherein accumulating, detecting, and asynchronously writing further includes processing the operations with a plurality of D-type flip-flops.

3. The method of claim 2, wherein processing further includes using at least one exclusive-or gate.

4. The method of claim 1, wherein accumulating, detecting, and asynchronously writing further includes processing the operations within a graphics engine or in cooperation with the graphics engine.

5. The method of claim 1, wherein representing further includes mapping the plurality of regions to locations within the display device.

6. The method of claim 1, wherein representing further includes representing each of the plurality of regions with a same number of the plurality of pixels.

7. The method of claim 1, wherein representing further includes representing a number of the plurality of regions with different numbers of the plurality of pixels from what represents other ones of the plurality of regions.

8. A computer-readable medium having instructions embedded thereon, the instructions when executed by a computer performing the method of:

segmenting a frame buffer into regions, each region having a configurable shape and having pixels that span multiple rows of that shape;

buffering writes to a first one of the regions within the frame buffer; and

asynchronously updating the first one of the regions to a display once a different write to a different one of the regions is detected.

9. The medium of claim 8 further comprising instructions for mapping each region to a different location within the display.

10. The medium of claim 8, wherein segmenting further includes representing the configurable shape as a rectangle having a same dimension for each of the regions.

11. The medium of claim 8, wherein segmenting further includes representing the configurable shape differently with different dimensions for different ones of the regions.

12. An apparatus, comprising:

a frame buffer comprising a plurality of regions, wherein each region represents a respective plurality of pixels on a display device that spans more than one row of the respective plurality of the pixels and a shape of each region is configurable; and

logic to accumulate writes by a graphics engine to one of the plurality of regions in the frame buffer until the graphics engine writes to another region of the plurality of regions in the frame buffer, wherein when the graphics engine writes to the another region, the logic is to cause the one region to be asynchronously written to the display device.

13. The apparatus of claim 12, wherein the logic comprises a plurality of D-type flip-flops.

14. The apparatus of claim 13, wherein one of the plurality of D-type flip-flops is to receive input of a region number of the one region and a clock input to be active when each of the respective writes occurs.

15. The apparatus of claim 13, wherein at least one of the D-type flip-flops includes an exclusive-or gate.

16. The apparatus of claim 12, wherein the logic is to identify each of the plurality of regions via region numbers or identifiers that is to be supplied by the graphics engine.

17. The apparatus of claim 12, wherein the logic is to flag each of the plurality of regions when a write is performed on that region by the graphics engine, and wherein the flag indicates a modification.

18. The apparatus of claim 17, wherein the logic is to clear the flag for a particular region if that region is written to the display device.

19. A system, comprising:

a frame buffer comprising a plurality of regions, wherein each region represents a respective plurality of pixels on a display device that spans more than one row of the respective plurality of the pixels and a shape of each region is configurable;

logic to accumulate writes by a graphics engine to one of the plurality of regions in the frame buffer until the graphics engine writes to another region of the plurality of regions in the frame buffer, wherein when the graphics engine writes to the another region, the logic is to cause the one region to be asynchronously written to the display device; and

the display device to visually present the plurality of pixels and the writes associated therewith.

20. The system of claim 19, wherein the logic includes a plurality of D-type flip-flops.

21. The system of claim 19, wherein the logic is to convert addresses associated with writes to the frame buffer received from the graphics engine to specific ones of the plurality of regions.

22. The system of claim 19, wherein logic further includes:

snoop logic to cause the frame buffer to accumulate the writes; and

scan-out logic to asynchronously write the one region to the display device.