Arc fault detector responsive to patterns in interval to interval change in integrated sensed current values

• US 7,349,188 B2
• Filed: 06/06/2005
• Issued: 03/25/2008
• Est. Priority Date: 06/06/2005
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Pahl, Birger, Zuercher, Joseph C., Hastings, Jerome K.
• Primary Examiner(s): Sherry; Michael
• Assistant Examiner(s): BAUER, SCOTT ALLEN
• Application Number:
  US11/146,416
• Publication Number:
  US 20060274460A1
• Time in Patent Office: 1,023 Days
• Field of Search: 361/42
• US Class Current: 361/42
• CPC Class Codes: H02H 1/0015 Using arc detectors
• CPC Class Codes: H02H 1/04 Arrangements for preventing response to transient abnormal conditions, e.g. to lightning or to short duration over voltage or oscillations; Damping the influence of dc component by short circuits in ac networks

Abstract

An arc fault detector analyzes patterns in a sequence of counts of interval to interval increases or decreases in integrated current for patterns characteristic of arc faults. In AC systems, the interval can be a full cycle or in an alternative embodiment, the changes in integrated current for positive and negative half cycles are separately determined and then interleaved before the change counts are calculated. The count sequence is reset when patterns characteristic of phenomena other than an arc fault are detected to avoid nuisance trips.

Claims

1. An arc fault detector for an electrical system, the arc fault detector comprising:

a sensed current signal generator generating from current flowing in the electrical system a sensed current signal;

an integrator repetitively integrating an absolute value of the sensed current signal over equal time intervals to generate integrated sensed current values;

a change indicator generating for each most recently completed time interval, a change indication when the integrated sensed current value for the most recently completed time interval changes by at least a threshold amount from the integrated sensed current value for the preceding time interval;

a summer repetitively summing for each most recently completed time interval the number of change indications generated over a selected number of the most recently completed time intervals to generate a change count;

a memory storing the change counts for the selected most recently completed intervals in a sequence of change counts; and

a processor comprising;

detector means generating an arc signal in response to patterns in the sequence of change counts indicative of an arc; and

reset means clearing the memory of the sequence of change counts in response to predetermined other patterns in the sequence of change counts indicative of events other than an arc.

2. The arc fault detector of claim 1 wherein the detector means generates an arc signal in response to a pattern in the sequence of change counts comprising the presence of each of a plurality of specified change counts.

3. The arc fault detector of claim 2 wherein the memory stores the change count for the six most recently completed intervals to form the sequence of change counts and wherein the plurality of specified change counts is four.

4. The arc fault detector of claim 3 wherein the four different change counts comprise 1, 2, 3, and 4.

5. The arc fault detector of claim 4 wherein the detector means generates an arc fault signal when the change counts 1, 2, 3, and 4 appear in any order sequentially or non-sequentially within the sequence of change counts except the sequence 1, 2, 3, 4 unless followed by a change count of four.

6. The arc fault detector of claim 5 wherein the reset means comprises a timer that cleans the sequence of changes in the change court when the change counts 1, 2, 3, and 4 do not occur within a specified time period.

7. The arc fault detector of claim 1 wherein the reset means comprises a timer that initiates a time period in response to certain change counts in the sequence of change counts and that clears the sequence of change counts in the memory upon timing out of the time period.

8. The arc fault detector of claim 1 wherein the reset means clears the memory of the sequence of change counts in response to a first selected number of consecutive time intervals in which the integrated sensed current values are below a minimum value.

9. The arc fault detector of claim 1 wherein the reset means clears the memory of the sequence of change counts in response to a second selected number of consecutive time intervals in which the sensed current signal exceeds an inrush current value.

10. The arc fault detector of claim 1 wherein the reset means clears the memory of the sequence of change counts in response to a pattern in the sequence of change counts indicative of a moving dimmer.

11. The arc fault detector of claim 10 in which the pattern in the sequence of change counts indicative of a moving dimmer comprises a certain number of consecutive intervals in which the integrated sensed current values increase or decrease and the sensed current values approaching a zero crossing are indicative of a sine wave.

12. The arc fault detector of claim 1 wherein the reset means clears the memory of the sequence of change counts in response to certain repetitive patterns in the sequence of change counts.

13. The arc fault detector of claim 12 wherein the reset means clears the memory in response to a repetitive pattern within the sequence of change counts.

14. The arc fault detector of claim 12 wherein the reset means clears the memory in response to a repetitive pattern in a selected number of sequences of change counts.

15. The arc fault detector of claim 1 in which the reset means clears the memory in response to a zero in the sequence of change counts.

16. The arc fault detector of claim 1 wherein the electrical system is an AC electrically system and the time interval is a half cycle;

the sensed current signal generator generates a positive half cycle sensed current signal and a negative half cycle sensed current signal;

the integrator repetitively integrates an absolute value of the positive half cycle sensed current signal over each positive half cycle to generate positive half cycle integrated sensed current values and repetitively integrates an absolute value of the negative half cycle sensed current signal over each negative half cycle to generate negative half cycle integrated sensed current values;

the change indicator comprises a positive half cycle change indicator generating for each most recently completed positive half cycle a positive half cycle change indication when the positive half cycle integrated current value for the most recently completed positive half cycle changes by at least the threshold amount from the positive half cycle integrated current value for the preceding positive half cycle and a negative half cycle change indicator generating for each most recently completed negative half cycle a negative half cycle change indication when the negative half cycle integrated current value for the most recently completed negative half cycle changes by at least the threshold amount from the negative half cycle integrated current value for the preceding negative half cycle, and means interleaving the positive half cycle change indications and the negative half cycle change indications to generate interleaved positive half cycle and negative half cycle change indications; and

the summer repetitively sums for each most recently completed half cycle the number of interleaved positive half cycle and negative half cycle change indications generated over the predetermined number of positive half cycles and negative half cycles to generate the change count.

17. The arc fault detector of claim 16 wherein the reset means clears the memory of the sequence of counts in response to a pattern in the sequence of change counts indicative of a half wave load.

18. The arc fault detector of claim 17 wherein the pattern indicative of a half wave load in response to which the reset means clears the memory of the sequence of change counts comprises a plurality of consecutive integrated sensed current values above a first half wave value in one polarity half cycle and less than a second lower half wave value in the other polarity half cycle.

19. The arc fault detector of claim 1 wherein the electrical system is an AC electrical system and the time interval is one cycle.

20. The arc fault detector of claim 19 wherein the selected number of time intervals comprises six cycles.