Enhanced compliant probe card systems having improved planarity

• US 7,349,223 B2
• Filed: 06/16/2004
• Issued: 03/25/2008
• Est. Priority Date: 05/23/2000
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: NanoNexus, Inc.
• Inventors: Haemer, Joseph Michael, Chong, Fu Chiung, Modlin, Douglas N.
• Primary Examiner(s): Dinh, Tuan T.
• Assistant Examiner(s): NGUYEN, HOA CAO
• Application Number:
  US10/870,095
• Publication Number:
  US 20040223309A1
• Time in Patent Office: 1,378 Days
• Field of Search: 361767-771, 361/785, 361/787, 361/790, 361/803, 361/804, 324/754, 324/755, 324/758, 324/763, 324/765, 439/54, 439/169, 439/219, 439/912, 257/48, 438/14, 438/15, 295/93
• US Class Current: 361/767
• CPC Class Codes: G01R 1/06711 Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
• CPC Class Codes: G01R 1/06727 Cantilever beams
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: H05K 3/4092 Integral conductive tabs, i.e. conductive parts partly detached from the substrate
• CPC Class Codes: H05K 7/1061 co-operating by abutting
• CPC Class Codes: Y10S 439/912 with testing means
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part

Abstract

Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a stiffening structure and a compliant carrier structure, such as a decal or screen, which is fixedly attached to the probe chip substrate.

Claims

1. A test apparatus for an integrated circuit wafer, comprising:

a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface;

a probe chip substrate comprising a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection;

at least one intermediate connector located between the motherboard substrate and the probe chip substrate, the intermediate connector comprising at least one electrically conductive connection between each of the plurality of electrical contacts on the probe chip substrate and each of the electrical conductors on the bottom surface of the motherboard substrate;

a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member; and

a stiffening ring fixedly attached to the probe chip substrate through the compliant member;

wherein the probe chip substrate and the stiffening ring are supported by the compliant member relative to the motherboard.

2. The test apparatus of claim 1, wherein the stiffening ring comprises any of:

a ceramic, a metal, a polymer, a reinforced polymer, a composite of any of a polymer, metal, and a ceramic having nano particles.

3. The test apparatus of claim 1, wherein the compliant member is fixedly attached to the connector surface of the probe chip substrate, and wherein the stiffening ring is fixedly attached to the compliant member.

4. The test apparatus of claim 1, wherein the compliant member is adhesively attached to the probe chip substrate.

5. The test apparatus of claim 1, wherein the stiffening ring is mechanically attached to the probe chip substrate.

6. The test apparatus of claim 1, wherein the stiffening ring is adhesively attached to the compliant member.

7. The test apparatus of claim 1, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.

8. The test apparatus of claim 7, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.

9. The test apparatus of claim 7, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.

10. The test apparatus of claim 1, wherein at least one of the electrical connections comprises a plurality of electrically conductive vias.

11. The test apparatus of claim 1, wherein the compliant member is attached to the connector surface of the probe chip substrate.

12. The test apparatus of claim 1, further comprising:

a stiffener plate fixedly attached to the top surface of the motherboard substrate.

13. The test apparatus of claim 1, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is attached to the peripheral region of the probe chip substrate.

14. The test apparatus of claim 1, wherein the intermediate connector comprises an interposer having a first plurality of compliant electrical contacts on a first surface and a second plurality of compliant electrical contacts on a second surface opposite the first surface.

15. The test apparatus of claim 1, further comprising:

a permanent electrical interface between the intermediate connector and the motherboard substrate.

16. The test apparatus of claim 15, wherein the permanent interface comprises any of a solder ball array, an anisotropic conductive film;

and a plurality of electrically conductive pins.

17. The test apparatus of claim 1, further comprising:

a planarity adjustment mechanism in which the planarity of the probe chip is adjustable relative to the motherboard substrate.

18. The test apparatus of claim 1, wherein the intermediate connector comprises a printed wiring board, and wherein the plurality of electrically conductive connections comprise vias having means for electrical connection to the probe chip and means for electrical connection to the motherboard.

19. The test apparatus of claim 18, wherein the means for electrical connection to the motherboard comprises an interposer.

20. The test apparatus of claim 18, wherein the means for electrical connection to the probe chip comprises an interposer.

21. The test apparatus of claim 1, wherein the intermediate connector comprises a Z-block, comprising a vertical translation substrate having a lower surface and an upper surface, and a plurality of electrically conductive connections which extend from the lower surface to the upper surface thereof, each of the electrically conductive connections comprising at least one electrically conductive via.

22. The test apparatus of claim 21, further comprising an interposer between the Z-block and the motherboard substrate.

23. The test apparatus of claim 21, further comprising an interposer between the Z-block and the probe chip substrate.

24. The test apparatus of claim 1, wherein the intermediate connector comprises an electrically conductive pin block having a plurality of holes defined between a lower surface and an upper surface thereof, and wherein the plurality of electrically conductive connections comprise pins extending through the plurality of holes, the pins comprising means for connection to the probe chip and means for connection to the motherboard.

25. The test apparatus of claim 24, wherein the means for electrical connection to the probe chip comprises any of a solder ball array, solder joints;

and a plurality of springs.

26. The test apparatus of claim 24, wherein the means for electrical connection to the motherboard comprises a pin grid array;

a pin socket array;

a solder joints; and

press fit pin connections.

27. A test apparatus for an integrated circuit wafer, the test apparatus connectable to a prober, comprising:

a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface;

a probe chip substrate having a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection, wherein the plurality of electrical contacts on the connector surface contact at least one of the plurality of electrical conductors on the bottom surface of the motherboard;

a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member; and

a stiffening ring attached to the probe chip substrate through the compliant member;

wherein the probe chip substrate and the stiffening ring are supported by the compliant member relative to the motherboard.

28. The test apparatus of claim 27, wherein the stiffening ring comprises any of a ceramic, a metal, and a polymer;

a reinforced polymer, and a composite of any of a polymer, metal, and a ceramic having nano particles.

29. The test apparatus of claim 27, wherein the compliant member is fixedly attached to the connector surface of the probe chip substrate, and wherein the stiffening ring is fixedly attached to the compliant member.

30. The test apparatus of claim 27, wherein the compliant, member is adhesively attached to the probe chip substrate.

31. The test apparatus of claim 27, wherein the stiffening ring is mechanically attached to the probe chip substrate.

32. The test apparatus of claim 27, wherein the stiffening ring is adhesively attached to compliant member.

33. The test apparatus of claim 27, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.

34. The test apparatus of claim 33, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.

35. The test apparatus of claim 33, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.

36. The test apparatus of claim 27, wherein at least one of the probe chip electrical connections comprises a plurality of electrically conductive vias.

37. The test apparatus of claim 27, wherein the compliant member is attached to the connector surface of the probe chip substrate.

38. The test apparatus of claim 27, further comprising:

a stiffener plate fixedly attached to the top surface of the motherboard substrate.

39. The test apparatus of claim 27, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is attached to the peripheral region of the probe chip substrate.

40. The test apparatus of claim 27, further comprising:

a planarity adjustment mechanism in which the planarity of the probe chip substrate is adjustable relative to the prober.

41. A decal assembly process, comprising the steps of:

providing a probe chip substrate having an outer periphery and an inner region, and having a probe surface and a connector surface, a plurality of probe springs on the probe surface within the inner region, and a plurality of electrical contacts on the connector surface within the inner region, wherein each of the probe springs is electrically connected to at least one electrical contact;

applying an adhesive to the outer periphery of the connector surface of the probe chip substrate;

providing a mounting ring having an opening defined there through, the opening larger than the outer periphery of the probe chip substrate;

attaching a compliant member across the mounting ring;

adhesively attaching the compliant member to the applied adhesive on the outer periphery of the probe chip substrate; and

attaching a stiffening ring to any, of the probe chip substrate and the compliant member.

42. The process of claim 41, wherein the stiffening ring comprises any of a ceramic, a metal, and a polymer;

a reinforced polymer; and

a composite of any of a polymer, metal, and a ceramic having nano particles.

43. The process of claim 41, wherein the compliant member is fixedly attached to the connector surface of the probe chip substrate, and wherein the stiffening ring is fixedly attached to the compliant member.

44. The process of claim 41, wherein the stiffening ring is mechanically attached to the probe chip substrate.

45. The process of claim 41, wherein the stiffening ring is adhesively attached to the compliant member.

46. A test method for an integrated circuit wafer, comprising the steps of:

providing a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface;

providing a probe chip substrate comprising a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection;

locating at least one intermediate connector between the motherboard substrate and the probe chip substrate, the intermediate connector comprising at least one electrically conductive connection between each of the plurality of electrical contacts on the probe chip substrate and each of the electrical conductors on the bottom surface of the motherboard substrate;

attaching a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member; and

fixedly attaching a stiffening ring to the probe chip substrate through the compliant member;

wherein the probe chip substrate and the stiffening ring are supported by the compliant member relative to the motherboard.