Charge-trapping memory device and methods for its manufacturing and operation

• US 7,349,254 B2
• Filed: 05/31/2006
• Issued: 03/25/2008
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Qimonda Flash GmbH & Co. KG.
• Inventors: Prasad, Tholasampatti Subramanian Sudhindra
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US11/444,289
• Publication Number:
  US 20070280002A1
• Time in Patent Office: 664 Days
• Field of Search: 365/185.29, 365/185.03, 365/185.09, 365/185.24, 365/185.05, 365/185.18
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

A charge-trapping memory device includes an array of non-volatile memory cells. The array has at least a first sector and a second sector. Each sector includes a multiplicity of memory cells. Each memory cell is adapted to trap an amount of charge indicative of a programming state. A control circuit is operationally connected to the array and is adapted to access a memory cell of the array by means of storing charge in or removing charge from the memory cell. A disturb detection circuit is operationally connected to the array or the control circuit and is adapted to detect a disturbance level of the first sector based on a disturbance caused by accessing at least one memory cell of the second sector. A disturb leveling circuit is operationally connected to the array and the disturb detection circuit and is adapted to backup the programming state of memory cells of the first sector if the detected disturbance level exceeds a predefined threshold.

Claims

1. A charge-trapping memory device, comprising

an array of non-volatile memory cells, the array comprising at least a first sector and a second sector, each sector comprising a plurality of memory cells, each memory cell adapted to trap an amount of charge indicative of a programming state;

a control circuit operationally connected to the array and adapted to access a memory cell of the array by storing charge in or removing charge from the memory cell;

a disturb detection circuit operationally connected to the array or the control circuit and adapted to detect a disturbance level of the first sector based on a disturbance caused by accessing at least one memory cell of the second sector; and

a disturb leveling circuit operationally connected to the array and the disturb detection circuit and adapted to backup the programming state of memory cells of the first sector if the detected disturbance level exceeds a predefined threshold.

2. The charge-trapping memory device according to claim 1, wherein:

the control circuit is adapted to access memory cells of the array in order to erase, program or read the programming state of the memory cells; and

erasing, programming or reading of memory cells of the second sector disturbs the programming state of memory cells of the first sector.

3. The charge-trapping memory device according to claim 1, wherein

at least one first memory cell of the first sector and at least one second memory cell of the second sector are coupled to a common bitline or wordline;

the control circuit is adapted to charge the common bitline or wordline in order to access the first cell; and

charging the common bitline or wordline disturbs the second memory cell.

4. The charge-trapping memory device according to claim 1, wherein the disturb detection circuit is adapted to detect a number of accesses to the second sector and to perform a predefined action if a predefined number of accesses has been reached.

5. The charge-trapping memory device according to claim 4, wherein:

the number of accesses is indicative of the disturbance level of the first sector; and

the disturb leveling circuit is adapted to backup the programming state of memory cells of the first sector if the number of accesses exceeds the predefined number.

6. The charge-trapping memory device according to claim 4, wherein:

the disturb detection circuit is further adapted to detect a number of bit failures in the first sector of memory cells if the number of accesses exceeds the predefined number; and

the disturb leveling circuit is adapted to backup the programming state of memory cells of the first sector if the detected number of bit failures exceeds the predefined threshold.

7. The charge-trapping memory device according to claim 6, wherein each sector of the array is associated with a counter adapted to store the number of bit failures in the associated sector.

8. A charge-trapping memory device, comprising:

at least two sectors, each sector comprising a data area and redundancy area, each area comprising a plurality of non-volatile memory cells, each memory cell including a charge-trapping layer;

a bit failure detector operationally connected to a first sector and adapted to detect a number of bit failures of the data area of the first sector based on data stored in the corresponding redundancy area, the bit failures being caused by accessing memory cells of a second sector; and

a controller operationally connected to the first sector and the bit failure detector and adapted to copy data stored in the data area of the first sector to another storage location if the number of bit failures is greater than a predefined threshold.

9. The charge-trapping memory device according to claim 8, wherein the controller is further adapted to recycle the memory cells of the first sector after copying the data stored in the first sector to the other storage location.

10. The charge-trapping memory device according to claim 9, wherein the controller is adapted to recycle the memory cells of the first sector by erasing or programming the memory cells to the predefined threshold level.

11. The charge-trapping memory device according to claim 9, wherein the controller is adapted to copy back the data to the first sector after copying the data to the other storage location and recycling the memory cells of the first sector.

12. The charge-trapping memory device according to claim 11, wherein the controller is adapted to copy the data to a volatile buffer memory, recycle the memory cells of the first sector and copy back the data from the volatile buffer memory to the first sector.

13. The charge-trapping memory device according to claim 8, wherein the controller is adapted to copy the data to a third sector comprising a plurality of memory cells.

14. The charge-trapping memory device according to claim 8, wherein the charge-trapping layer comprises a nitride layer and the memory device is an NROM memory device.