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Circuit and method for adaptive incremental step-pulse programming in a flash memory device

  • US 7,349,263 B2
  • Filed: 05/02/2006
  • Issued: 03/25/2008
  • Est. Priority Date: 06/27/2005
  • Status: Active Grant
First Claim
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1. A nonvolatile memory device, comprising:

  • an array of nonvolatile memory cells; and

    a control circuit electrically coupled to said array of nonvolatile memory cells, said control circuit configured to perform a plurality of memory programming operations by driving a selected word line in said array with a first stair step sequence of program voltages having first step height and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell having a threshold voltage greater than or equal to a first verify voltage, driving the selected word line with a second stair step sequence of program voltages having a second step height lower than the first step height and using a verify voltage equivalent to the first verify voltage.

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