Circuit and method for adaptive incremental step-pulse programming in a flash memory device

• US 7,349,263 B2
• Filed: 05/02/2006
• Issued: 03/25/2008
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Jae-Yong, Kim, Soo-Han
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Lappas; Jason
• Application Number:
  US11/381,140
• Publication Number:
  US 20060291290A1
• Time in Patent Office: 693 Days
• Field of Search: 365/185.19
• US Class Current: 365/185.19
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.

Claims

1. A nonvolatile memory device, comprising:

an array of nonvolatile memory cells; and

a control circuit electrically coupled to said array of nonvolatile memory cells, said control circuit configured to perform a plurality of memory programming operations by driving a selected word line in said array with a first stair step sequence of program voltages having first step height and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell having a threshold voltage greater than or equal to a first verify voltage, driving the selected word line with a second stair step sequence of program voltages having a second step height lower than the first step height and using a verify voltage equivalent to the first verify voltage.

2. The nonvolatile memory device of claim 1, wherein said control circuit is further configured to perform a plurality of memory verify operations that are interleaved in time with the plurality of memory programming operations;

and

wherein a first duration of the memory verify operations associated with the first stair step sequence of program voltages is less than a second duration of the memory verify operations associated with the second stair step sequence of program voltages.

3. The nonvolatile memory device of claim 2, wherein a first interleaved sequence of program and verify operations associated with the first stair step sequence of program voltages commences with a program operation and terminates with a verify operation having the first duration;

and wherein a second interleaved sequence of program and verify operations associated with the second stair step sequence of program voltages commences with a verify operation having the second duration.

4. The nonvolatile memory device of claim 1, wherein said control circuit comprises:

a row decoder electrically coupled to a plurality of word lines in said array;

a voltage generator electrically coupled to said row decoder and responsive to a voltage control signal; and

a program controller configured to switch the voltage control signal from a first logic state to a second logic state in response to a first pass signal.

5. The nonvolatile memory device of claim 4, wherein said program controller is further configured to switch the voltage control signal from the second logic state to the first logic state in response to a last pass signal.

6. The nonvolatile memory device of claim 5, wherein said control circuit further comprises a sense amplifier and a pass/fail detector electrically coupled to an output of the sense amplifier and configured to generate the first and last pass signals.

7. The nonvolatile memory device of claim 6, wherein the sense amplifier is responsive to a sense amplifier enable signal generated by said program controller.

8. The nonvolatile memory device of claim 6, wherein the pass/fail detector comprises a first pass detector having OR logic therein and a last pass detector having AND logic therein.

9. The nonvolatile memory device of claim 3, wherein said control circuit comprises:

a row decoder electrically coupled to a plurality of word lines in said array;

a voltage generator electrically coupled to said row decoder and responsive to a voltage control signal; and

a program controller configured to switch the voltage control signal from a first logic state to a second logic state in response to a first pass signal.

10. The nonvolatile memory device of claim 9, wherein said program controller is further configured to switch the voltage control signal from the second logic state to the first logic state in response to a last pass signal.

11. The nonvolatile memory device of claim 10, wherein said control circuit further comprises a sense amplifier and a pass/fail detector electrically coupled to an output of the sense amplifier and configured to generate the first and last pass signals.

12. The nonvolatile memory device of claim 11, wherein the sense amplifier is responsive to a sense amplifier enable signal generated by said program controller.

13. The nonvolatile memory device of claim 11, wherein the pass/fail detector comprises a first pass detector having OR logic therein and a last pass detector having AND logic therein.

14. A nonvolatile memory device, comprising:

an array of nonvolatile memory cells; and

a control circuit electrically coupled to said array of nonvolatile memory cells,

said control circuit configured to perform a plurality of memory programming operations by driving a selected word line in said array with a stair step sequence of program voltages and further configured to generate a plurality of memory verify pulses that are interleaved in time with the plurality of memory programming operations, said plurality of memory verify pulses comprising first verify pulses having a first duration and second verify pulses having a second duration greater than the first duration.

15. The memory device of claim 14, wherein said control circuit is configured to switch from generating first verify pulses to generating second verify pulses in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell.

16. The nonvolatile memory device of claim 14, wherein said control circuit comprises:

a row decoder electrically coupled to a plurality of word lines in said array;

a voltage generator electrically coupled to said row decoder and responsive to a voltage control signal; and

a program controller configured to switch the voltage control signal from a first logic state to a second logic state in response to a first pass signal.

17. The nonvolatile memory device of claim 16, wherein said program controller is further configured to switch the voltage control signal from the second logic state to the first logic state in response to a last pass signal.