Memory device with a data hold latch
First Claim
1. A memory device comprising:
- a first write bit line;
a second write bit line, the second write bit line being a complementary bit line to the first write bit line;
a column of memory cells coupled to the first write bit line and the second write bit line;
a latch circuit having an input coupled to a data line and an output to provide a latched value dependent upon a value of the data line, the output is coupled to the first write bit line such that a value of the first write bit line is continuously determined by the output during memory device operation;
a first read bit line, the column of memory cells coupled to the first read bit line;
a second read bit line, the second read bit line being a complementary bit line to the first read bit line, the column of memory cells coupled to the second read bit line.
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Accused Products
Abstract
A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.
31 Citations
32 Claims
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1. A memory device comprising:
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a first write bit line; a second write bit line, the second write bit line being a complementary bit line to the first write bit line; a column of memory cells coupled to the first write bit line and the second write bit line; a latch circuit having an input coupled to a data line and an output to provide a latched value dependent upon a value of the data line, the output is coupled to the first write bit line such that a value of the first write bit line is continuously determined by the output during memory device operation; a first read bit line, the column of memory cells coupled to the first read bit line; a second read bit line, the second read bit line being a complementary bit line to the first read bit line, the column of memory cells coupled to the second read bit line. - View Dependent Claims (6, 7, 12, 13, 14, 15, 16, 17, 18, 29, 30)
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2. A memory device comprising:
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a bit line; a column of memory cells coupled to the bit line; a latch circuit having an input coupled to a data line and an output to provide a latched value dependent upon a value of the data line, the output is coupled to the bit line such that a value of the bit line is continuously determined by the output during memory device operation; wherein the latch includes a second input to receive a clock signal, wherein the output of the latch changes value dependent upon a value of the data line at a time determined by a change of state of the clock signal; a word line coupled to a memory cell of the column of memory cells to carry a write signal to the memory cell; word line generation circuitry having an output coupled to the word line to provide the write signal, the write generation circuitry including an input to receive a clock signal, wherein the write signal changes state at a time determined by a change of state of the clock signal received at the input of the write generation circuitry; wherein the clock signal received by the write generation circuitry and the clock signal received at the second input of the latch are generated from a common clock signal. - View Dependent Claims (3, 4, 5, 9, 10, 11)
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8. A memory device comprising:
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a bit line; a column of memory cells coupled to the bit line; a latch circuit having an input coupled to a data line and an output to provide a latched value dependent upon a value of the data line, the output is coupled to the bit line such that a value of the bit line is continuously determined by the output during memory device operation; a read bit line, the column of memory cells coupled to the read bit line; wherein the bit line is a write bit line; wherein the latch includes a pair of cross coupled inverters; wherein the output is coupled to an input of a first inverter of the pair and an output of the second inverter of the pair; wherein the latch includes a third inverter having an output connected to the output of the latch and an input connected to the input of the first inverter of the pair and the output of the second inverter of the pair.
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19. A method of operating a memory device comprising:
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operating a memory device including performing a plurality of reads via a read bit line and a complementary read bit line and a plurality of writes via a write bit line and a complementary write bit line to memory cells of a column of memory cells, wherein the read bit line and the complementary read bit line are coupled to the column of memory cells and the write bit line and the complementary write bit line are coupled to the column of memory cells; continuously controlling a value of the write bit line and the complementary write bit line with a first latch output and a second latch output, respectively, during the operating. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
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31. A memory device comprising:
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a plurality of pairs of complimentary bit lines, wherein each pair of the plurality is coupled to a column of memory cells; a plurality of latch circuits, each latch circuit having an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line; wherein for each latch of the plurality, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation; wherein the latch includes a second input to receive a clock signal, wherein the output of the latch changes value dependent upon a value of the data line at a time determined by a change of state of the clock signal.
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32. A memory device comprising:
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a first write bit line; a second write bit line, the second write bit line being a complementary bit line to the first write bit line; a column of memory cells coupled to the first write bit line and the second write bit line; a latch circuit having an input coupled to a data line, a first output to provide a first latched value dependent upon a value of the data line, a second output to provide a second latched value dependent upon a value of the data line, the first output is coupled to the first write bit line such that the value of the first write bit line changes if and only if the value of the first output changes during memory device operation, the second output is coupled to the second write bit line such that the value of the second write bit line changes if and only if the value of the second output changes during memory device operation; a read bit line, the column of memory cells coupled to the read bit line.
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Specification