Access circuit and method for allowing external test voltage to be applied to isolated wells

• US 7,349,273 B2
• Filed: 10/27/2006
• Issued: 03/25/2008
• Est. Priority Date: 12/29/2003
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zimlich, David A.
• Primary Examiner(s): PHAM, LY D
• Application Number:
  US11/588,989
• Publication Number:
  US 20070041232A1
• Time in Patent Office: 515 Days
• Field of Search: 365/72, 365/201, 365/175, 365/177, 365/191, 365/202, 257/499, 257/544
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Claims

1. A method of applying a test voltage to each of a plurality of circuit wells fabricated in a semiconductor substrate of an integrated circuit and isolated from each other, the method comprising:

applying a test voltage to the integrated circuit through an externally accessible terminal;

coupling the externally accessible terminal to one of the circuit wells while isolating the externally accessible terminal from the other circuit wells, the act of coupling the externally accessible terminal to one of the circuit wells comprising;

providing first and second transistors fabricated in respective wells of the substrate for each of the circuit wells, the first and second transistors having first source-drain regions interconnecting to each other and second source-drain regions coupled to the wells in which they are fabricated;

coupling the first and second transistors for each of the circuit wells between the externally accessible terminal and the respective circuit well;

applying signals to gate electrodes of the first and second transistors for the one circuit well that causes the first and second transistors to turn on; and

applying signals to gate electrodes of the first and second transistors for the other circuit wells that causes the first and second transistors to turn off.

2. The method of claim 1 wherein the semiconductor substrate comprises an n-type substrate, and the wells in which the first and second transistors are fabricated comprise p-type wells.

3. The method of claim 1 wherein the substrate comprises a p-type substrate, and the wells in which the first and second transistors are fabricated and the circuit wells comprise respective n-type wells.

4. The method of claim 1 wherein the integrated circuit comprises a memory integrated circuit.

5. The method of claim 4 wherein the memory circuit comprises a dynamic random access memory circuit.

6. The method of claim 1 wherein the well in which the first transistor is fabricated is different from the well in which the second transistor is fabricated.

7. The method of claim 1 wherein the first transistor is coupled in series with the second transistor.