Ultra-wideband communication apparatus and methods

• US 7,349,478 B2
• Filed: 11/12/2004
• Issued: 03/25/2008
• Est. Priority Date: 12/06/2001
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: Pulse-Link Incorporated
• Inventors: Lakkis, Ismail
• Primary Examiner(s): Payne, David C.
• Assistant Examiner(s): Wong, Linda
• Application Number:
  US10/988,373
• Publication Number:
  US 20050117557A1
• Time in Patent Office: 1,229 Days
• Field of Search: 375/295, 375/149, 37524026-24028, 375/240.24, 375/316, 375/243, 375/246, 375/265, 375/262, 704/501, 704/504, 358/539, 714/755, 714/759
• US Class Current: 375/240.27
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/1185 wherein the parity-check matrix comprises a part with a double-diagonal
• CPC Class Codes: H04B 1/71635 Transmitter aspects H04B1/7174 takes precedence
• CPC Class Codes: H04B 1/719 Interference-related aspects
• CPC Class Codes: H04L 1/0006 by adapting the transmission format
• CPC Class Codes: H04L 1/0026 Transmission of channel quality indication
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0668 Orthogonal systems, e.g. using Alamouti codes
• CPC Class Codes: H04L 2025/03414 Multicarrier
• CPC Class Codes: H04L 2025/03426 transmission using multiple-input and multiple-output channels
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 27/0004 using wavelets

Abstract

Apparatus and methods of ultra-wideband (UWB) communication are provided. In one embodiment, an ultra-wideband transmitter includes a processor configured to generate data for transmission in the form of a plurality of ultra-wideband pulses. The transmitter includes a FEC encoder that generates a code word based on the data. The FEC includes a plurality of cyclic shift registers configured to receive and process the data, a plurality of fixed connections between each of the plurality of cyclic shift registers and a plurality of XOR gates communicating with the plurality of fixed connections. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Claims

1. An ultra-wideband transmitter, comprising:

a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband pulses by the transmitter, and

a forward error correction encoder configured to generate a code word based on the data, the forward error correction encoder comprising;

a plurality of cyclic shift registers configured to receive and process the data;

a plurality of fixed connections between each of the plurality of cyclic shift registers,

a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates;

further comprising a register configured to store an output of each of the plurality of XOR gates; and

;

further comprising a register XOR gate communicating with the register, the register XOR gate configured to XOR an output of the register with a delayed version of the output of the register.

2. An ultra-wideband transmitter, comprising:

a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband pulses by the transmitter, and

a forward error correction encoder configured to generate a code word based on the data, the forward error correction encoder comprising;

a plurality of cyclic shift registers configured to receive and process the data;

a plurality of fixed connections between each of the plurality of cyclic shift registers,

a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates;

wherein the code word is generated using a parity matrix, and the parity matrix comprises a matrix of cyclic matrices; and

wherein a first of the cyclic matrices is generated from an identity matrix and a permutation vector, and each of the subsequent cyclic matrices are generated by rotating the previous cyclic matrix.

3. An ultra-wideband transmitter, comprising:

a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband pulses by the transmitter, and

a forward error correction encoder configured to generate a code word based on the data, the forward error correction encoder comprising;

a plurality of cyclic shift registers configured to receive and process the data;

a plurality of fixed connections between each of the plurality of cyclic shift registers,

a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates;

wherein the plurality of fixed connections are arranged based on a dual diagonal matrix and a cyclic matrix.