Frequency shift keying signaling for integrated circuits

• US 7,349,488 B1
• Filed: 04/10/2003
• Issued: 03/25/2008
• Est. Priority Date: 04/10/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Watson, James A., Margolese, Michael A.
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): WILLIAMS, LAWRENCE B
• Application Number:
  US10/412,533
• Time in Patent Office: 1,811 Days
• Field of Search: 375/224, 375/272, 375/344, 375/279, 375/280, 375/379, 375/269, 326 21- 35, 326/99, 257/275, 329/300, 332/100, 340/825.58
• US Class Current: 375/272
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/10 Frequency-modulated carrier systems, i.e. using frequency-shift keying H04L27/32 takes precedence

Abstract

The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. A first integrated circuit has transmitter circuit that generates frequency shift keying signals using digital data and a second integrated circuit has a receiver circuit for recovering the digital data from the frequency shift keying signals.

Claims

1. A system for communicating between two integrated circuits, comprising:

a first integrated circuit having a transmitter circuit for converting digital data into a frequency modulated signal, the first integrated circuit positioned on a first printed circuit board for transmission of the frequency modulated signal via a transmission line to a second integrated circuit;

the frequency modulated signal representing the digital data as the frequency modulated signal includes signal components having frequencies representing logic states of the digital data;

the second integrated circuit electrically coupled to the transmission line and having a receiver circuit for converting the frequency modulated signal back to the digital data, the second integrated circuit positioned on the first printed circuit board or on a second printed circuit board, wherein the second printed circuit board is connected to the first printed circuit board via a common backplane;

the frequency modulated signal including an amplitude frequency shift keying (AFSK) signal the modulation circuit comprising;

a frequency generator configured to generate a plurality of clock signals, each clock signal of the plurality of clock signals having a predetermined frequency;

a modulation circuit configured to receive the digital data and at least one of the plurality of clock signals and configured to generate the AFSK signal;

a first multiplexer configured to select a clock signal of the plurality of clock signals using a first bit of the digital data;

an amplifier connected to the first multiplexer for amplifying the selected clock signal; and

a second multiplexer connected to the amplifier and configured to select the selected clock signal, the second multiplexer controlled by a second bit of the digital data.

2. The system of claim 1 wherein the receiver circuit, comprises a bandpass filter coupled to an envelope detector.

3. The system of claim 1 wherein the frequency generator comprises a ring oscillator having a plurality of inverters for generating a clock signal of the plurality of clock signals.

4. The system of claim 1 wherein the frequency generator comprises a ring oscillator, comprising a plurality of inverters, coupled to flip-flop for generating the plurality of clock signals.

5. The system of claim 1 wherein the receiver circuit comprises:

an amplitude detection circuit configured to determine an indication of amplitude of a plurality of amplitudes of the AFSK signal;

a frequency detection circuit, comprising a counting circuit for determining a number of edges in the AFSK signal in a predetermined time period, wherein the number gives an indication of a frequency of the AFSK signal; and

a mapping circuit, comprising digital logic, receiving the indication of amplitude and the indication of the frequency and generating at least one bit of the digital data.

6. The system of claim 5 wherein the amplitude detection circuit comprises a differential amplifier coupled to a current mirror circuit and a latch.

7. The system of claim 5 wherein the counting circuit comprises a first counter comprising, a first plurality of flip-flops, configured to count a number of rising edges and a second counter, comprising a second plurality of flip-flops, configured to count a number of falling edges.

8. The system of claim 7 further comprising:

a symbol clock received from the transmitter circuit for resetting the first and second plurality of flip-flops; and

a delay circuit for delaying the AFSK signal with respect to the symbol clock.

9. The system of claim 5 wherein the counting circuit comprises an adder circuit configured to count the number of edges.

10. The system of claim 1 wherein the first integrated circuit is selected from the group consisting of a field programmable gate array, a programmable logic device, digital signal processor, a microprocessor, an audio processor, a video graphics processor, and an applications specific integrated circuit.

11. A method for communicating between two integrated circuits, comprising:

transforming digital data from a first integrated circuit into a frequency modulated signal for transmission of the frequency modulated signal via a transmission line to a second integrated circuit;

the first integrated circuit being positioned on a first printed circuit board;

the frequency modulated signal representing the digital data as the frequency modulated signal includes signal components having frequencies representing logic states of the digital data;

transmitting the frequency modulated signal to the second integrated circuit electrically coupled to the transmission line, the second integrated circuit being positioned on the first printed circuit board or on a second printed circuit board, wherein the second printed circuit board is connected to the first printed circuit board via a common backplane;

recovering the digital data from the frequency modulated signal in the second integrated circuit;

the frequency modulated signal comprises an amplitude frequency shift keying (AFSK) signal, wherein the AFSK signal is formed by a modulation circuit comprising;

a first multiplexer configured to select a clock signal of a plurality of clock signals using a first bit of the digital data;

an amplifier connected to the first multiplexer for amplifying the selected clock signal; and

a second multiplexer connected to the amplifier and configured to select the selected clock signal, the second multiplexer being controlled by a second bit of the digital data signal; and

the recovering including;

demodulating the frequency modulated signal to produce a plurality of intermediary bits; and

mapping the plurality of intermediary bits to the digital data.

12. The method of claim 11 wherein the frequency modulated signal includes amplitude modulation, wherein the amplitude modulation is determined from at least one bit of the digital data.

13. The method of claim 12 wherein the recovering comprises detecting an amplitude of the frequency modulated signal.

14. The method of claim 11 wherein the transforming comprises:

generating a plurality of clock signals having different frequencies; and

selecting a clock signal of the plurality of clock signals based on one or more bits of the digital data.

15. The method of claim 14 further comprising forwarding a symbol clock signal of the plurality of clock signals from the first integrated circuit to the second integrated circuit.

16. The method of claim 11 wherein demodulating the frequency modulated signal comprises determining a number of edges in the frequency modulated signal.

17. The method of claim 11 further comprising, generating a plurality of clock signals by a plurality of ring oscillators for use in transforming digital data from the first integrated circuit into the frequency modulated signal.

18. A system for communicating data between a plurality of components in an integrated circuit, comprising:

a first component of the plurality of components having an output circuit for converting digital data of the first component into a frequency modulated signal, wherein the output circuit comprises;

a first multiplexer configured to select a clock signal of a plurality of clock signals using a first bit of the digital data;

an amplifier connected to the first multiplexer for amplifying the selected clock signal; and

a second multiplexer connected to the amplifier and configured to select the selected clock signal, the second multiplexer being controlled by a second bit of the digital data signal;

the frequency modulated signal representing the digital data as the frequency modulated signal includes signal components having frequencies representing logic states of the digital data;

a second component of the plurality of components having an input circuit for converting the frequency modulated signal back to the digital data, wherein the input circuit comprises a multiplexer configured to select the selected clock signal; and

an electrical connection in the integrated circuit coupled to the first component and the second component for communicating between the input and the output circuits;

the input circuit including;

a frequency detection circuit having a counter circuit configured to determine an indication of a number of edges of the frequency modulated signal; and

a mapping circuit having digital logic for receiving the indication and generating at least one bit of the digital data.

19. The system of claim 18 wherein a component of the plurality of components includes a Configurable Logic Block (CLB) or a Input/Output Block (IOB) of an FPGA.

20. The system of claim 18 wherein the output circuit comprises:

a modulation circuit configured to receive the digital data and at least one of a plurality of clock signals and to generate the frequency modulated signal using the digital data.

21. The system of claim 20 further comprising:

a ring oscillator for generating a clock signal of the plurality of clock signals.

22. A system for communicating data between two integrated circuits, comprising:

a means for transforming digital data from a first integrated circuit into a frequency modulated signal, the first integrated circuit positioned on a first printed circuit board for transmission of the frequency modulated signal via a transmission line to a second integrated circuit, and wherein the means for transforming digital data includes a means for generating a plurality of clock signals with different frequencies;

the frequency modulated signal representing the digital data as the frequency modulated signal includes signal components having the frequencies representing logic states of the digital data;

the second integrated circuit being positioned on the first printed circuit board or on a second printed circuit board and electrically coupled to the transmission line, wherein the second printed circuit board is connected to the first printed circuit board via a common backplane;

a means in the second integrated circuit for recovering the digital data from the frequency modulated signal; and

wherein the frequency modulated signal comprises an amplitude frequency shift keying (AFSK) signal wherein the AFSK signal is formed by a modulation circuit comprising;

a first multiplexer configured to select a clock signal of a plurality of clock signals using a first bit of the digital data;

an amplifier connected to the first multiplexer for amplifying the selected clock signal; and

a second multiplexer connected to the amplifier and configured to select the selected clock signal, the second multiplexer being controlled by a second bit of the digital data signal;

the means in the second integrated circuit for recovering the digital data including;

a frequency detection circuit having a counter circuit configured to determine an indication of a number of edges of the frequency modulated signal; and

a mapping circuit having digital logic for receiving the indication and generating at least one bit of the digital data.