Memory based cross compare for cross checked systems

• US 7,350,026 B2
• Filed: 12/03/2004
• Issued: 03/25/2008
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: Thales SA
• Original Assignee: Thales SA
• Inventors: Barr, Stephen, Popescu, Mario, Trica, Alexander
• Primary Examiner(s): Shah; Sanjiv
• Assistant Examiner(s): Ayash; Marwan
• Application Number:
  US11/002,237
• Publication Number:
  US 20060123202A1
• Time in Patent Office: 1,208 Days
• Field of Search: 714/820, 714/819, 711/149
• US Class Current: 711/119
• CPC Class Codes: G06F 11/1633 using mutual exchange of the output between the redundant processing components
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/185 and the voting is itself performed redundantly

Abstract

A cross compare solution running in a multiprocessor configuration, using a multi-port RAM with built-in logic. This provides for a fast and simple data cross compare medium. The multi-port RAM unit can be plugged into the motherboard of the main processor unit, requiring no external hardware or wiring. A method and a system for cross compare has a first layer of buffers with a first storage area for storing information from the first processor and a second storage area for storing information from the second processor, and a second layer of buffers with a third and fourth storage areas, where each storage area stores information from the first and second storage areas. The first, second, third, and fourth storage areas have one or more buffers allocated only for its respective storage area.

Claims

1. A cross compare system for a multi-processor computer having at least a first and a second processor, comprising:

a multiport RAM comprising a first layer of buffers and a second layer of buffers, wherein both the first processor and the second processor are connected to the multiport RAM;

the first layer of buffers comprising a first storage area of the multiport RAM for storing information from the first processor and a second storage area of the multiport RAM for storing information from the second processor;

the second layer of buffers comprising a third storage area of the multiport RAM for storing the information from said first storage area and the information from said second storage area, and a fourth storage area of the multiport RAM for storing the information from said first storage area and the information from said second storage area, the information from said first storage area and said second storage area being automatically transferred to said third storage area and said fourth storage area;

wherein each of said first, second, third, and fourth storage areas of the multiport RAM comprise a respective at least one buffer allocated only for its storage area, wherein simultaneous access to any one memory locations in the first, second, third and fourth storage areas is not possible;

wherein said first processor reads the information from said third storage area and compares data stored in the third storage area from the first storage area with data stored in the third storage area from the second storage area to determine if the information stored in said third storage from the first storage area is substantially identical to the information stored in the third storage area from the second storage area; and

wherein said second processor reads the information from said fourth storage area and compares data stored in the fourth storage area from the first storage area with data stored in the fourth storage area from the second storage area to determine if the information stored in said fourth storage area from the first storage area is substantially identical to the information stored in the fourth storage area from the second storage area.

2. The cross compare system for a multi-processor computer according to claim 1, wherein the first layer of buffers are write-only and wherein the second layer of buffers are read-only buffers.

3. The cross compare system for a multi-processor computer according to claim 2, wherein the first and the second processors write data into the first layer buffers asynchronously and wherein the data from the first layer buffer is transferred into the second layer buffers synchronously.

4. The cross compare system for a multi-processor computer according to claim 1, wherein when the data being compared in said first processor does not match, isolating said first processor, and wherein when the data being compared in said second processor does not match, isolating said second processor.

5. The cross compare system for a multi-processor computer according to claim 1, wherein a timeout is provided for reading data for the cross comparison from the second layer buffers by the first and the second processors.

6. The cross compare system for a multi-processor computer according to claim 1, wherein the first and second processors are synchronized before the cross-comparison, and wherein the synchronization is detected via polling of the second layer buffers by each of the first and second processors.

7. The cross compare system for a multi-processor computer according to claim 1, wherein each of the first and the second processors is one of a Central Processing Unit, a microprocessor, a Run Time Vital Control Unit, and a Multiprocessor Unit.

8. The cross compare system for a multi-processor computer according to claim 1, wherein the first and second layer buffers form a Multi-port Random Access Memory that is plugged into a backplane of the first and second processors connecting to a standard or a non-standard bus.

9. The cross compare system for a multi-processor computer according to claim 1, wherein FPGAs or ASICs perform required logic operations for the first and second layer buffers, and wherein for a storage area from the first and second layer buffers allocated to a particular processor from the first and second processors, an individual FPGA or ASIC is provided.

10. The cross compare system for a multi-processor computer according to claim 9, wherein for each of the FPGAs or ASICs an individual power source is provided.

11. The cross compare system for a multi-processor computer according to claim 1, wherein each of said third and fourth storage areas comprises a first register for the data from the first storage area and a second register for the data from the second storage area, and each of said first and second processors compares data from the first register with data from the second register, and wherein a successful cross-compare is declared when the data in the first register is identical to the data in the second register, where both the first and second registers are in a storage area allocated exclusively for a comparing processor.

12. The cross compare system for a multi-processor computer according to claim 11, wherein said data stored in the first and second registers are input to a computing operation or an output of the computing operation.

13. A method of performing a cross compare for a multi-processor computer having at least three processors, where each of said at least three processors uses a separate memory location within a multiport RAM and where each of said at least three processors is provided with an individual port and each of the individual ports is provided with a buffer of a plurality of first layer buffers within the multiport RAM, the method comprising ordered steps of:

(a) each processor writing information to be cross compared to the buffer of said plurality of first layer buffers within the multiport RAM corresponding to the port of the respective processor;

(b) transferring information written to all of said plurality of the first layer buffers to a plurality of second layer buffers within the multiport RAM, each buffer of the plurality of second layer buffers providing a storage area for every buffer of the first plurality of buffers, and a buffer of the plurality of second layer buffers being provided for each of the plurality of processors, wherein simultaneous access to a memory location in any one of the plurality of first layer buffers and the plurality of second layer buffers is not possible;

(c) each processor reading the information from a respective buffer of the plurality of second layer buffers within the multiport RAM; and

(d) each processor comparing the information read from its buffer of the plurality of second layer buffers within the multiport RAM, declaring a successful cross compare if information from another processor matches information from the comparing processor, wherein said at least three processors are synchronized before executing the transfer of information in the ordered step (b).

14. A method of performing a cross compare according to claim 13, further comprising an ordered step of:

(e) determining whether there is additional information to be cross-compared, and if so, repeating the steps with the additional information, beginning at step (a).

15. A method of performing a cross compare according to claim 13, further comprising detecting successful synchronization by each of said plurality of processors via polling of its corresponding buffer from the plurality of the second buffers, and wherein when after a predetermined period of time, the successful synchronization between all of said plurality of processors is not detected by a processor from the plurality of processors, executing a timeout operation and performing the comparison of the information by the processor.

16. A method of performing a cross compare according to claim 13, wherein said synchronization is performed before the ordered step (a) so as to write the information to be cross compared to said plurality of first layer buffers simultaneously.

17. A method of performing a cross compare according to claim 13, wherein said synchronization is performed after the ordered step (a) so as to write the information to be cross compared to said plurality of first layer buffers asynchronously.

18. A method of performing a cross compare according to claim 13, wherein said synchronization of data and said cross-comparing is performed twice per each processor cycle, one at a beginning of the processor cycle for input data and the other at an end of the processor cycle for output data.

19. A method of performing a cross compare according to claim 18, wherein said comparison of the output data is performed after computational processing in each of the plurality of processors.

20. A method of performing a cross compare according to claim 19, wherein said transfer of data in the ordered steps (a) and (b) and said computational processing is performed by a plurality of FPGAs or ASICs, and wherein at least one FPGA or ASIC is provided for each of the at least three processors.

21. A method of performing a cross compare according to claim 13, wherein each one of the second layer buffers comprises at least one separate register for each processor from said at least three processors.

22. A cross compare system for a multi-processor computer having at least a first, a second processor, and a third processor, comprising:

a multiport RAM comprising a first layer of buffers and a second layer of buffers, wherein each of the first processor, the second processor and the third processor are connected to the multiport RAM;

the first layer of buffers comprising a first storage area for storing information from the first processor, a second storage area for storing information from the second processor, and a third storage area for storing information from the third processor;

the second layer of buffers comprising a fourth storage area, a fifth storage area, and a sixth storage area, each storing the information from said first storage area, the information from said second storage area, and the information from said third storage area, the information from said first layer of buffers is automatically transferred to said second layer of buffers;

wherein each of said first to sixth storage areas of the multiport RAM comprises at least one buffer allocated only for its storage area, wherein simultaneous access to any one memory location in the first, second, third, fourth, fifth and sixth storage areas is not possible;

wherein said first, second, and third processor reads the information from said fourth, fifth, and sixth storage area, respectively, and compares the information stored in its respective storage area to determine if the information of a comparing processor is substantially identical to the information of the other two processors;

and wherein a successful cross-compare is declared when the information of the comparing processor matches the information of at least one of the other two processors.

23. The cross compare system for a multi-processor computer according to claim 22, wherein the first layer of buffers are write-only and wherein the second layer of buffers are read-only buffers.

24. The cross compare system for a multi-processor computer according to claim 23, wherein the first, second, and third processors write data into the first layer buffers asynchronously and wherein the data from the first layer buffer is transferred into the second layer buffers synchronously.

25. The cross compare system for a multi-processor computer according to claim 22, wherein when the information from the comparing processor does not match the information of the two other processors, the successful cross-compare cannot be declared and the comparing processor is isolated.

26. The cross compare system for a multi-processor computer according to claim 25, wherein a timeout is provided for reading data for the cross comparison from the second layer buffers by the first, second, and third processors.

27. The cross compare system for a multi-processor computer according to claim 22, wherein the first, second, and third processors are synchronized before the cross-comparison, and wherein the synchronization is detected via polling of the second layer buffers by each of the first, second, and third processors.

28. The cross compare system for a multi-processor computer according to claim 22, wherein each of the first, second, and third processors is one of a Central Processing Unit, a microprocessor, a Run Time Vital Control Unit, and a Multiprocessor Unit.

29. The cross compare system for a multi-processor computer according to claim 22, wherein the first and second layer buffers form a Multi-port Random Access Memory that is plugged into a backplane of the first, second, and third processors connecting to a standard or a non-standard bus.

30. The cross compare system for a multi-processor computer according to claim 22, wherein FPGAs or ASICs perform required logic operations for the first and second layer buffers, and wherein for a storage area from the first and second layer buffers allocated to a particular processor from the first, second, and third processors, an individual FPGA or ASIC is provided.

31. The cross compare system for a multi-processor computer according to claim 30, wherein for each of the FPGAs or ASICs an individual power source is provided.

32. The cross compare system for a multi-processor computer according to claim 22, wherein each storage area, namely said fourth, fifth, and six storage areas, of the second layer of buffers comprises a register, namely a first, a second, and a third register, for each processor, namely the first, second, and the third processors, wherein the first processor compares the information stored in the first register of the fourth storage area with the information stored in the second register and with the information stored in the third register of the fourth storage area, wherein the second processor compares the information stored in the second register of the fifth storage area with the information stored in the first register and with the information stored in the third register, of the fifth storage area, and wherein the third processor compares the information stored in the third register of the sixth storage area with the information stored in the first register and with the information stored in the second register, of the sixth storage area.

33. The cross compare system for a multi-processor computer according to claim 32, wherein for each of said first, second, and third processors, an individual port is provided for transferring information from its respective storage area of the second layer of buffers to a respective processor for performing said comparison.

34. The cross compare system for a multi-processor computer according to claim 32, wherein said data stored in the first, second, and third registers are inputs for executing at least one computing operation or outputs of the at least one computing operation.