Tightly coupled accelerator

• US 7,350,055 B2
• Filed: 01/31/2005
• Issued: 03/25/2008
• Est. Priority Date: 10/20/2004
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.), University of Michigan
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Flautner, Krisztian, Clark, Nathan, Mahlke, Scott, Biles, Stuart D.
• Primary Examiner(s): DOLLINGER, TONIA LYNN MEONSKE
• Application Number:
  US11/046,555
• Publication Number:
  US 20060095721A1
• Time in Patent Office: 1,149 Days
• Field of Search: 717/136, 717/148, 717/124, 712/208, 712/227, 712/34, 712/218
• US Class Current: 712/34
• CPC Class Codes: G06F 8/44 Encoding
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.

Claims

1. Apparatus for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs within said program, said apparatus comprising:

an operand store operable to store operand data;

an execution unit coupled to said operand store and responsive to an individual program instruction within said program;

(i) to read one or more input operand values from said operand store;

(ii) to perform a data processing operation specified by said individual program instruction upon said one or more input operand values to generate one or more output operand values; and

(iii) to write said one or more output operand values to said operand store; and

an accelerator unit coupled to said operand store and triggered by reaching an execution point within said program corresponding to a sequence of individual program instructions corresponding to a computational subgraph within said program to apply a selected one of a plurality of predetermined sets of configuration data inputs to said accelerator to configure said accelerator;

(iv) to read one or more input operands from said operand store;

(v) to perform an accelerated data processing operation specified by said sequence of program instructions upon said one or more input operands to generate one or more output operand values and at least one intermediate operand value being an operand value generated by one of said individual program instructions within said sequence of program instructions and determined not to be referenced outside of said sequence of program instructions; and

(vi) to write said one or more output operand values to said operand store with said at least one intermediate operand value not being written to said operand store,

wherein said accelerator unit has a plurality of stages each containing one or more primitive operator units with configurable interconnect logic configured to pass operand values between primitive operator units of different stages.

2. Apparatus as claimed in claim 1, wherein said accelerator unit comprises a plurality of primitive operator units and said plurality of predetermined sets of configuration data specify interconnections to be made between said primitive operator units.

3. Apparatus as claimed in claim 2, wherein said plurality of predetermined sets of configuration data specify operations to be performed by said primitive operator units.

4. Apparatus as claimed in claim 1, wherein said plurality of predetermined sets of configuration data are generated by parsing said program to identify said sequences of individual program instructions corresponding to computational subgraphs using one or more of:

a compiler operable prior to execution of said program;

a software thread executing upon said apparatus; and

a hardware unit within said apparatus.

5. Apparatus as claimed in claim 1, wherein said accelerator unit has more operand input ports than operand output ports.

6. Apparatus as claimed in claim 5, wherein said accelerator unit has four operand input ports and two operand output ports.

7. Apparatus as claimed in claim 1, wherein within a stage said primitive operator units have common functionality.

8. Apparatus as claimed in claim 1, wherein the number of primitive operator units decreases with successive stages.

9. Apparatus as claimed in claim 1, wherein alternating stages include primitive operator units providing addition and logical operations and primitive operator units providing logical operations but not addition operations.

10. Apparatus as claimed in claim 1, wherein said plurality of stages are operable to complete said accelerated processing operation in fewer processing cycles of said apparatus than would be taken for separate individual execution of program instructions within said sequence of program instruction with said execution unit.

11. Apparatus as claimed in claim 10, wherein said plurality of stages are operable to complete said accelerated processing operation in one processing cycle of said apparatus.

12. Apparatus as claimed in claim 1, wherein said operand store is one of a register file and an operand stack memory.

13. A method of processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs within said program, said method comprising:

storing operand data within an operand store;

in response to an individual program instruction within said program using an execution unit coupled to said operand store;

(i) to read one or more input operand values from said operand store;

(ii) to perform a data processing operation specified by said individual program instruction upon said one or more input operand values to generate one or more output operand values; and

(iii) to write said one or more output operand values to said operand store; and

triggered by reaching an execution point within said program corresponding to a sequence of individual program instructions corresponding to a computational subgraph within said program, applying a selected one of a plurality of predetermined sets of configuration data inputs to an accelerator unit coupled to said operand store to control said accelerator unit;

(iv) to read one or more input operands from said operand store;

(v) to perform an accelerated data processing operation specified by said sequence of program instructions upon said one or more input operands to generate one or more output operand values and at least one intermediate operand value being an operand value generated by one of said individual program instructions within said sequence of program instructions and determined not to be referenced outside of said sequence of program instructions; and

(vi) to write said one or more output operand values to said operand store with said at least one intermediate operand value not being written to said operand store,

wherein said accelerator unit has a plurality of stages each containing one or more primitive operator units with configurable interconnect logic that passes operand values between primitive operator units of different stages.

14. Apparatus for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs within said program, said apparatus comprising:

an operand store operable to store operand data;

an execution unit coupled to said operand store and responsive to an individual program instruction within said program;

(i) to read one or more input operand values from said operand store;

(ii) to perform a data processing operation specified by said individual program instruction upon said one or more input operand values to generate one or more output operand values; and

(iii) to write said one or more output operand values to said operand store; and

an accelerator unit coupled to said operand store and triggered by reaching an execution point within said program corresponding to a sequence of individual program instructions corresponding to a computational subgraph within said program to apply a selected one of a plurality of predetermined sets of configuration data inputs to said accelerator to configure said accelerator;

(iv) to read one or more input operands from said operand store;

(v) to perform an accelerated data processing operation specified by said sequence of program instructions upon said one or more input operands to generate one or more output operand values and at least one intermediate operand value being an operand value generated by one of said individual program instructions within said sequence of program instructions and determined not to be referenced outside of said sequence of program instructions; and

(vi) to write said one or more output operand values to said operand store with said at least one intermediate operand value not being written to said operand store,

wherein said accelerator unit has four operand input ports and two operand output ports.

15. A method of processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs within said program, said method comprising:

storing operand data within an operand store;

in response to an individual program instruction within said program using an execution unit coupled to said operand store;

(i) to read one or more input operand values from said operand store;

(ii) to perform a data processing operation specified by said individual program instruction upon said one or more input operand values to generate one or more output operand values; and

(iii) to write said one or more output operand values to said operand store; and

triggered by reaching an execution point within said program corresponding to a sequence of individual program instructions corresponding to a computational subgraph within said program, applying a selected one of a plurality of predetermined sets of configuration data inputs to an accelerator unit coupled to said operand store to control said accelerator unit;

(iv) to read one or more input operands from said operand store;

(v) to perform an accelerated data processing operation specified by said sequence of program instructions upon said one or more input operands to generate one or more output operand values and at least one intermediate operand value being an operand value generated by one of said individual program instructions within said sequence of program instructions and determined not to be referenced outside of said sequence of program instructions; and

(vi) to write said one or more output operand values to said operand store with said at least one intermediate operand value not being written to said operand store,

wherein said accelerator unit has four operand input ports and two operand output ports.