System and method for testing a memory using DMA

• US 7,350,109 B2
• Filed: 11/14/2003
• Issued: 03/25/2008
• Est. Priority Date: 11/14/2003
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Pomaranski, Ken G., Shidla, Dale J., Barr, Andrew H.
• Primary Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US10/714,302
• Publication Number:
  US 20050120268A1
• Time in Patent Office: 1,593 Days
• Field of Search: 714/27, 714/9
• US Class Current: 714/27
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Abstract

A computer system that includes a processor, a first bus coupled to the processor, a memory controller coupled to the first bus, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the first bus, and a test module coupled to the first I/O controller is provided. The test module is configured to cause tests to be performed on the memory using the first bus.

Claims

1. A computer system comprising:

a processor configured to execute an operating system;

a first bus coupled to the processor;

a memory; and

a core electronics complex including;

a memory controller coupled to the first bus and the memory;

a first input/output (I/O) controller coupled to the first bus and configured to couple to a first set of one or more I/O devices using a first connection; and

a test module coupled to the first I/O controller using a second connection that is separate from the first connection and the first bus;

wherein the test module is configured to provide test transactions to the first I/O controller using the second connection, and wherein the first I/O controller is configured to provide the test transactions to the memory controller using the first bus to cause tests to be performed on the memory.

2. The computer system of claim 1 further comprising:

the operating system;

wherein the processor is configured to cause the operating system to be booted, and wherein the test module is configured to cause the tests to be performed on the memory using the first bus subsequent to the operating system being booted.

3. The computer system of claim 1 further comprising:

the operating system;

wherein the processor is configured to cause the operating system to be executed, and wherein the test module is configured to cause the tests to be performed on the memory using the first bus during execution of the operating system.

4. The computer system of claim 1 wherein the first bus comprises a system bus.

5. The computer system of claim 1 further comprising:

a second bus; and

a second set of one or more I/O devices coupled to the second bus;

wherein the core electronics complex includes a second I/O controller coupled to the first bus and the second bus.

6. The computer system of claim 1 wherein the test transactions include read and write transactions.

7. The computer system of claim 6 wherein the read and write transactions comprise direct memory access (DMA) transactions.

8. The computer system of claim 1 further comprising:

a bus bridge coupled to the first bus and the first I/O controller; and

wherein the first I/O controller is configured to provide the test transactions to the bus bridge, and wherein the bus bridge is configured to provide the test transactions to the memory controller using the first bus.

9. A method performed by a computer system that includes a memory comprising:

selecting a portion of the memory for testing during operation of the computer system;

generating a test transaction in a test module coupled to an input/output (I/O) controller using a first connection that is separate from a second connection that is configured to couple the I/O controller to one or more I/O devices and separate from a system bus coupled to a processor, the test module and the I/O controller included in a chipset coupled to the memory and the system bus;

providing the test transaction from the test module to the I/O controller using the first connection;

providing the test transaction from the I/O controller to a memory controller; and

providing the test transaction from memory controller to the portion using direct memory access (DMA).

10. The method of claim 9 further comprising:

detecting an error that occurs in response to the test transaction; and

performing a remedial action in response to detecting the error.

11. The method of claim 9 further comprising:

providing the test transaction from the I/O controller to a bus bridge included in the chipset;

providing the test transaction from the bus bridge to the system bus; and

providing the test transaction from the system bus to the memory controller.

12. The method of claim 11 further comprising:

storing information in the memory in response to the test transaction being a write transaction.

13. The method of claim 11 further comprising:

in response to the test transaction being a read transaction;

providing information associated with the test transaction from the portion to the memory controller;

providing the information from the memory controller to the system bus;

providing the information from the system bus to the bus bridge;

providing the information from the bus bridge to the I/O controller; and

providing the information from the I/O controller to the test module.

14. The method of claim 9 further comprising:

providing the test transaction from the I/O controller to a system controller included in the chipset; and

providing the test transaction from the system controller to the memory contro1ler.

15. A computer system comprising:

a processor configured to execute an operating system;

a bus coupled to the processor;

a memory;

a core electronics complex including;

a system controller coupled to the bus and the memory;

an input/output (I/O) controller coupled to the system controller and configured to couple to a set of one or more I/O devices using a first connection; and

a test module coupled to the I/O controller using a second connection that is separate from the first connection and the bus;

wherein the test module is configured to provide test transactions to the I/O controller using the second connection, and wherein the I/O controller is configured to provide the test transactions to a memory controller using the bus to cause tests to be performed on the memory using direct memory access (DMA).

16. The computer system of claim 15 further comprising:

the operating system;

wherein the processor is configured to cause the operating system to be booted, and wherein the test module is configured to cause the tests to be performed on the memory using DMA subsequent to the operating system being booted.

17. The computer system of claim 15 further comprising:

the operating system;

wherein the processor is configured to cause the operating system to be executed, and wherein the test module is configured to cause the tests to be performed on the memory using DMA during execution of the operating system.

18. The computer system of claim 15 wherein the bus comprises a system bus.

19. The computer system of claim 15 wherein the test transactions include read and write transactions.

20. The computer system of claim 19 wherein the read and write transactions comprise direct memory access (DMA) transactions.