Decoding LDPC (low density parity check) code with new operators based on min* operator

• US 7,350,130 B2
• Filed: 12/20/2004
• Issued: 03/25/2008
• Est. Priority Date: 08/15/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US11/017,403
• Publication Number:
  US 20050149844A1
• Time in Patent Office: 1,191 Days
• Field of Search: 714/804, 714/801
• US Class Current: 714/758
• CPC Class Codes: H03M 13/1117 using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
• CPC Class Codes: H03M 13/112 with correction functions for the min-sum rule, e.g. using an offset or a scaling factor
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/251 with block coding
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing
• CPC Class Codes: H03M 13/658 Scaling by multiplication or division
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0058 Block-coded modulation

Abstract

Decoding LDPC (Low Density Parity Check) code with new operators based on min* operator. New approximate operators are provided that may be employed to assist in calculating one or a minimum value (or a maximum value) when decoding various coded signals. In the context of LDPC decoding that involves both bit node processing and check node processing, either of these new operators (i.e., the min† (min-dagger) operator or the min′ (min-prime) operator) may be employed to perform the check node processing that involves updating the edge messages with respect to the check nodes. Either of these new operators, min† operator or min′ operator, is shown herein to be a better approximate operator to the min** operator.

Claims

1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

a bit node processor that is operable to;

receive a plurality of bit metrics; and

perform bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes; and

a check node processor that is operable to perform check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes by performing min†

(min-dagger) processing or min′

(min-prime processing).

2. The decoder of claim 1, further comprising:

a metric generator that is operable to;

receive I, Q (In-phase, Quadrature) values corresponding to a symbol of the LDPC coded signal; and

generate a plurality of symbol metrics from the I, Q values; and

a symbol node calculator functional block that is operable to generate the plurality of bit metrics from the plurality of symbol metrics.

3. The decoder of claim 1, further comprising:

a hard limiter that is operable to receive soft output from the bit node processor that corresponds to most recently updated plurality of edge messages with respect to the plurality of bit nodes and to make best estimates of bits of a symbol of the LDPC coded signal using the soft output.

4. The decoder of claim 3, further comprising:

a syndrome calculation functional block that is operable to receive the best estimates of bits of the symbol of the LDPC coded signal from the hard limiter and is operable to determine whether each of a plurality of syndromes of an LDPC code by which the LDPC coded signal is generated is substantially equal to zero within a degree of precision.

5. The decoder of claim 1, wherein the check node processor further comprises a min†

functional block that is operable to;

perform min†

processing on a plurality of inputs to generate a min†

result;

include a min* (min-star) functional block that is operable to perform min* processing on the plurality of inputs to generate a min* result;

when the min* result is greater than or equal to zero within a predetermined degree of precision, the min†

functional block is operable to output the min* result as the min†

result; and

when the min* result is less than zero within a predetermined degree of precision, the min†

functional block is operable to output a value of zero as the min†

result.

6. The decoder of claim 1, wherein the check node processor further comprises a min′

functional block that is operable to;

perform min′

processing on a plurality of inputs thereby to generate a min′

result;

include a min functional block that is operable to perform min processing on the plurality of inputs to generate a min result;

include a min* (min-star) functional block that is operable to perform min* processing on the plurality of inputs to generate a min* result;

when the min result is greater than zero within a predetermined degree of precision, the min′

functional block is operable to output the min* result as the min′

result; and

when the min result is less than or equal to zero within the predetermined degree of precision, the min′

functional block is operable to output a value of zero as the min′

result.

7. The decoder of claim 1, wherein:

the LDPC coded signal is a variable code rate signal;

the first symbol of the LDPC coded signal has a first code rate; and

the second symbol of the LDPC coded signal has a second code rate.

8. The decoder of claim 1, wherein:

the LDPC coded signal is a variable modulation signal;

the first symbol of the LDPC coded signal has a first modulation having a first constellation shape and a corresponding first mapping; and

the second symbol of the LDPC coded signal has a second modulation having a second constellation shape and a corresponding second mapping.

9. The decoder of claim 1, wherein:

the decoder is operable to decode LDPC coded signals that are compliant with at least one of DVB-S2 (Digital Video Broadcasting Project—

Satellite Version

     2) draft standard and recommended practices provided by IEEE (Institute of Electrical &

Electronics Engineers) P802.3an (10 GBASE-T) Task Force.

10. A method for decoding an LDPC (Low Density Parity Check) coded signal, the method comprising:

receiving a plurality of bit metrics;

performing bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes; and

performing check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes by performing min†

(min-dagger) processing or min′

(min-prime processing).

11. The method of claim 10, further comprising:

receiving I, Q (In-phase, Quadrature) values corresponding to a symbol of the LDPC coded signal;

generating a plurality of symbol metrics from the I, Q values; and

generating the plurality of bit metrics from the plurality of symbol metrics.

12. The method of claim 10, further comprising:

receiving soft output that corresponds to most recently updated plurality of edge messages with respect to the plurality of bit nodes; and

making best estimates of bits of a symbol of the LDPC coded signal using the soft output.

13. The method of claim 12, further comprising:

receiving best estimates of bits of the symbol of the LDPC coded signal; and

determining whether each of a plurality of syndromes of an LDPC code by which the LDPC coded signal is generated is substantially equal to zero within a degree of precision.

14. The method of claim 10, further comprising:

performing min†

processing on a plurality of inputs to generate a min†

result there from;

performing min* processing on the plurality of inputs to generate a min* result there from;

when the min* result is greater than or equal to zero within a predetermined degree of precision, outputting the min* result as the min†

result; and

when the min* result is less than zero within a predetermined degree of precision, outputting a value of zero as the min†

result.

15. The method of claim 10, further comprising:

performing min′

processing on a plurality of inputs thereby generating a min′

result there from;

performing min processing on the plurality of inputs thereby generating a min result there from;

performing min* processing on the plurality of inputs thereby generating a min* result there from;

when the min result is greater than zero within a predetermined degree of precision, outputting the min* result as the min′

result; and

when the min result is less than or equal to zero within the predetermined degree of precision, outputting a value of zero as the min′

result.

16. The method of claim 10, wherein:

the LDPC coded signal is a variable code rate signal;

the first symbol of the LDPC coded signal has a first code rate; and

the second symbol of the LDPC coded signal has a second code rate.

17. The method of claim 10, wherein:

the LDPC coded signal is a variable modulation signal;

the first symbol of the LDPC coded signal has a first modulation having a first constellation shape and a corresponding first mapping; and

the second symbol of the LDPC coded signal has a second modulation having a second constellation shape and a corresponding second mapping.

18. The method of claim 10, wherein:

the method is operable to decode LDPC coded signals that are compliant with at least one of DVB-S2 (Digital Video Broadcasting Project—

Satellite Version

     2) draft standard and recommended practices provided by IEEE (Institute of Electrical &

Electronics Engineers) P802.3an (10 GBASE-T) Task Force.

19. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

a bit node processor that is operable to;

receive a plurality of bit metrics; and

perform bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes; and

a check node processor that is operable to perform check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes by performing mint (min-dagger) processing or min′

(min-prime processing); and

wherein;

the LDPC coded signal is a variable code rate signal; and

the LDPC coded signal is a variable modulation signal.

20. A method for decoding an LDPC (Low Density Parity Check) coded signal, the method comprising:

receiving a plurality of bit metrics;

performing bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes; and

performing check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes by performing min†

(min-dagger) processing or min′

(min-prime processing); and

wherein;

the LDPC coded signal is a variable code rate signal; and

the LDPC coded signal is a variable modulation signal.