Method and apparatus for placement and routing cells on integrated circuit chips

• US 7,350,173 B1
• Filed: 01/23/2003
• Issued: 03/25/2008
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synplicity, Inc. (Synopsys Incorporated)
• Inventors: McElvain, Ken R., Ang, Roger P., McElvain, Kenneth S.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US10/351,094
• Time in Patent Office: 1,888 Days
• Field of Search: 716 7- 14, 716/15
• US Class Current: 716/114
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell. Timing is analyzed using a route of the wire connecting the first cell and the second cell to select a second path from the set of paths before a cell is placed on the second path.

Claims

1. A method to layout an integrated circuit, the method comprising:

analyzing timing to identify a set of cells on a path;

splitting the path into segments at a plurality of nets that includes determining the plurality of nets of the path;

generating a plurality of placement designs for the path, wherein each of the placement designs is generated from placing and routing cells of a first segment of the path near a first location that includes placing a cell of the first segment at a permissible location out of a plurality of permissible locations;

routing the cell from the permissible location; and

determining a timing parameter associated with the cell already placed and routed, and subsequently, after the routing of the cells of the first segment, placing and routing cells of a second segment of the path near a second location, the first segment and the second segment being connected by one of the plurality of nets;

routing at least one of the nets of the path for each of the plurality of placement designs; and

selecting a first design from the plurality of placement designs, wherein said selecting is based on actual routes of the at least one of the nets routed for each of the plurality of placement designs.

2. A method as in claim 1 wherein the plurality of nets are determined according to drive strength of corresponding nets.

3. A method as in claim 1 further comprising:

resizing a driver of the first design to increase drive strength of a wire of the first design.

4. A method as in claim 3 wherein the driver overlaps with a cell after said resizing.

5. A method as in claim 1 further comprising:

inserting a cell to buffer a wire of the first design.

6. A method as in claim 5 wherein, after said inserting, the cell to buffer the wire overlaps with a cell that is previously placed.

7. A machine readable medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to layout an integrated circuit, the method comprising:

analyzing timing to identify a set of cells on a path;

splitting the path into segments at a plurality of nets that includes determining the plurality of nets of the path;

generating a plurality of placement designs for the path, wherein each of the placement designs is generated from placing and routing cells of a first segment of the path near a first location that includes placing a cell of the first segment at a permissible location out of a plurality of permissible locations;

routing the cell from the permissible location; and

determining a timing parameter associated with the cell already placed and routed, and subsequently, after the routing of the cells of the first segment, placing and routing cells of a second segment of the path near a second location, the first segment and the second segment being connected by one of the plurality of nets;

routing at least one of nets of the path for each of the plurality of placement designs; and

selecting a first design from the plurality of placement designs, wherein said selecting is based on actual routes of the at least one of nets routed for each of the plurality placement designs.

8. A medium as in claim 7 wherein the plurality of nets are determined according to drive strength of corresponding nets.

9. A medium as in claim 7 wherein the method further comprises:

resizing a driver of the first design to increase drive strength of a wire of the first design.

10. A medium as in claim 9 wherein the driver overlaps with a cell after said resizing.

11. A medium as in claim 7 wherein the method further comprises:

inserting a cell to buffer a wire of the first design.

12. A medium as in claim 11 wherein, after said inserting, the cell to buffer the wire overlaps with a cell that is previously placed.

13. A digital processing system to layout an integrated circuit, the digital processing system comprising:

mean for analyzing timing to identify a set of cells on a path;

means for splitting the path into segments that includes means for determining the plurality of nets of the path;

means for generating a plurality of placement designs for the path, wherein each of the placement designs is generated by means for placing and routing cells of a

first segment of the path near a first location that includes means for placing a cell of the first segment at a permissible location out of a plurality of permissible locations;

means for routing the cell from the permissible location; and

means for determining a timing parameter associated with the cell already placed and routed, and means for subsequently, after the routing of the cells of the first segment, placing and routing cells of a second segment of the path near a second location, the first segment and the second segment being connected by one of the plurality of nets;

means for routing at least one of nets of the path for each of the plurality of placement designs; and

means for selecting a first design from the plurality of placement designs, wherein said selecting is based on actual routes of the at least one of nets routed for each of the plurality of placement designs.

14. A digital processing system as in claim 13 wherein the plurality of nets are determined according to drive strength of corresponding nets.

15. A digital processing system as in claim 13 further comprising:

means for resizing a driver of the first design to increase drive strength of a wire of the first design.

16. A digital processing system as in claim 15 wherein the driver overlaps with a cell after the drive is resized.

17. A digital processing system as in claim 13 further comprising:

means for inserting a cell to buffer a wire of the first design.

18. A digital processing system as in claim 17 wherein, after the cell is inserted, the cell to buffer the wire overlaps with a cell that is previously placed.