Post passivation interconnection schemes on top of the IC chips
First Claim
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1. A method for fabricating a chip comprising:
- providing a silicon substrate, an ESD circuit in or on said silicon substrate, a driver, receiver or I/O circuit in or on said silicon substrate, a first internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit and to a first terminal of said driver, receiver or I/O circuit, and wherein said ESD circuit is connected, in parallel with said driver, receiver or I/O circuit, to said first interconnecting structure, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said driver, receiver or I/O circuit, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said first internal circuit, wherein said first, second and third interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process, and a passivation layer over said dielectric layer; and
forming a fourth interconnecting structure over said passivation layer, wherein said second terminal is connected to said first internal circuit through, in sequence, said second interconnecting structure, said fourth interconnecting structure and said third interconnecting structure, and wherein said forming said fourth interconnecting structure comprises;
forming a first metal layer;
after said forming said first metal layer, forming a patterned photoresist layer;
after said forming said patterned photoresist layer, electroplating a second metal layer;
after said electroplating said second metal layer, removing said patterned photoresist layer; and
after said removing said patterned photoresist layer, etching said first metal layer.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
31 Claims
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1. A method for fabricating a chip comprising:
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providing a silicon substrate, an ESD circuit in or on said silicon substrate, a driver, receiver or I/O circuit in or on said silicon substrate, a first internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit and to a first terminal of said driver, receiver or I/O circuit, and wherein said ESD circuit is connected, in parallel with said driver, receiver or I/O circuit, to said first interconnecting structure, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said driver, receiver or I/O circuit, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said first internal circuit, wherein said first, second and third interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process, and a passivation layer over said dielectric layer; and forming a fourth interconnecting structure over said passivation layer, wherein said second terminal is connected to said first internal circuit through, in sequence, said second interconnecting structure, said fourth interconnecting structure and said third interconnecting structure, and wherein said forming said fourth interconnecting structure comprises; forming a first metal layer; after said forming said first metal layer, forming a patterned photoresist layer; after said forming said patterned photoresist layer, electroplating a second metal layer; after said electroplating said second metal layer, removing said patterned photoresist layer; and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for fabricating a chip comprising:
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providing a silicon substrate, multiple devices in and on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, and a passivation layer over said dielectric layer, wherein said passivation layer comprises oxide and nitride; and forming a second interconnecting structure over said passivation layer, wherein said forming said second interconnecting structure comprises; forming a first metal layer; after said forming said first metal layer, forming a patterned photoresist layer; after said forming said patterned photoresist layer, electroplating a second metal layer; after said electroplating said second metal layer, removing said patterned photoresist layer; and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 28, 29, 30, 31)
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17. A method for fabricating a chip comprising:
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providing a silicon substrate, multiple devices in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, and a passivation layer over said first metallization structure, an opening in said passivation layer exposing a pad of said first metallization structure, wherein said passivation layer comprises oxide and nitride; and forming a second metallization structure over said pad, wherein said forming said second metallization structure comprises; forming a first metal layer; after said forming said first metal layer, forming a patterned photoresist layer; after said forming said patterned photoresist layer, electroplating a second metal layer; after said electroplating said second metal layer, removing said patterned photoresist layer; and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification