Forming nonvolatile phase change memory cell having a reduced thermal contact area

• US 7,351,992 B2
• Filed: 08/15/2007
• Issued: 04/01/2008
• Est. Priority Date: 01/19/2005
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): Tran; Thien F
• Application Number:
  US11/839,490
• Publication Number:
  US 20070272913A1
• Time in Patent Office: 230 Days
• Field of Search: 257 2- 5, 257/41, 257/42, 257/E31.029
• US Class Current: 257/5
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a layer in a pillar-shaped section of a memory cell is etched laterally, decreasing its cross-section. In this way the cross section of the contact area between the heater layer and the phase change material is reduced. In preferred embodiments, the laterally etched layer is the heater layer or a sacrificial layer. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.

Claims

1. A monolithic three dimensional phase change memory array comprising:

a) a first memory level, the first memory level comprising;

i) a plurality of substantially parallel first conductors formed at a first height above a substrate;

ii) a plurality of substantially parallel second conductors formed at a second height, the second height above the first height;

iii) a plurality of first diodes, each disposed between one of the first conductors and one of the second conductors;

iv) a plurality of heater layers, each disposed between one of the first conductors and one of the second conductors and each having an upper surface having a first area;

v) a plurality of phase change elements, each having a lower surface having a second area,

wherein at least a part of the lower surface of each phase change element is in contact with the upper surface of the adjacent heater layer and

wherein the first area is smaller than the second area; and

b) at least a second memory level monolithically formed on the first memory level.

2. The monolithic three dimensional phase change memory array of claim 1 wherein the phase change elements comprise a chalcogenide material.

3. The monolithic three dimensional phase change memory array of claim 2 wherein the chalcogenide material comprises a GST material.

4. The monolithic three dimensional phase change memory array of claim 3 wherein the GST material comprises Ge₂Sb₂Te₅.

5. The monolithic three dimensional phase change memory array of claim 1 wherein the first diodes are p-i-n diodes.

6. The monolithic three dimensional phase change memory array of claim 5 wherein the first diodes reside in vertically oriented pillars.

7. The monolithic three dimensional phase change memory array of claim 1 wherein the substrate comprises monocrystalline silicon.

8. The monolithic three dimensional phase change memory array of claim 1 wherein the second conductors are substantially perpendicular to the first conductors.

9. The monolithic three dimensional phase change memory array of claim 1 wherein at least some of the first or second conductors comprise titanium tungsten or tungsten.

10. The monolithic three dimensional phase change memory array of claim 1 wherein the second memory level comprises a plurality of substantially parallel third conductors formed at a third height, the third height above the second height.

11. The monolithic three dimensional phase change memory array of claim 10 wherein the second memory level comprises a plurality of second diodes.

12. The monolithic three dimensional phase change memory array of claim 11 wherein the second memory level further comprises a plurality of substantially parallel fourth conductors formed at a fourth height, the fourth height above the third height.

13. The monolithic three dimensional phase change memory array of claim 12 wherein each of the second diodes is disposed between one of the third conductors and one of the fourth conductors.

14. The monolithic three dimensional phase change memory array of claim 11 wherein each of the second diodes is disposed between one of the second conductors and one of the third conductors.