Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures

• US 7,352,034 B2
• Filed: 08/25/2005
• Issued: 04/01/2008
• Est. Priority Date: 08/25/2005
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Mandelman, Jack Allan, Booth, Roger Allen Jr., Tonti, William Robert
• Primary Examiner(s): Baumeister; B. William
• Assistant Examiner(s): Gumedzoe; Peniel M
• Application Number:
  US11/211,956
• Publication Number:
  US 20070045748A1
• Time in Patent Office: 950 Days
• Field of Search: 438/480, 438/481, 257/E21.561, 257/E21.562, 257/E21.563
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of forming a semiconductor structure having FinFET'"'"'s and planar devices, such as MOSFET'"'"'s, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Claims

1. A method of making a semiconductor structure, the method comprising:

etching a first trench in a mask on a substrate;

partially filling the first trench with a first epitaxial semiconductor layer;

implanting ions into at least the first epitaxial semiconductor layer;

after the ions are implanted, depositing a second epitaxial semiconductor layer on the first epitaxial semiconductor layer in the first trench to define a semiconductor fin having a channel region;

forming a gate structure intersecting the channel region of the semiconductor fin; and

supporting the semiconductor fin with the mask while forming the gate structure.

2. The method of claim 1 wherein partially filling the first trench further comprises:

performing a selective epitaxial growth process that deposits a semiconductor constituting the first epitaxial semiconductor layer with a greater growth rate on horizontal surfaces than on vertical surfaces.

3. The method of claim 1 wherein forming the gate structure further comprises:

etching a second trench in the mask extending to the substrate, the second trench exposing the channel region; and

forming the gate structure in the second trench.

4. The method of claim 3 further comprising:

doping the exposed channel region; and

supporting the semiconductor fin with the mask while doping the exposed channel region.

5. The method of claim 3 wherein forming the gate structure further comprises:

forming a first gate in a first portion of the second trench flanking a first sidewall of the channel region; and

forming a second gate in a second portion of the second trench flanking a second sidewall of the channel region, the first gate being electrically isolated from the second gate.

6. The method of claim 5 further comprising:

forming a first gate dielectric on the first sidewall before forming the first gate; and

forming a second gate dielectric on the second sidewall before forming the second gate.

7. The method of claim 1 wherein the gate structure is formed by a damascene process.

8. The method of claim 1 wherein the semiconductor fin is formed by a damascene process.

9. The method of claim 1 further comprising:

forming a planar device adjacent to the semiconductor fin.

10. The method of claim 9 wherein the planar device is a metal oxide semiconductor field effect transistor.

11. The method of claim 1 wherein the substrate is monocrystalline and the trench extends to the substrate, and partially filling the first trench further comprises:

using the substrate as a monocrystalline seed for forming the first epitaxial semiconductor layer.

12. The method of claim 1 wherein implanting ions into at least the first epitaxial semiconductor layer further comprises:

implanting ions with a concentration profile partially in the first epitaxial semiconductor layer and partially in the substrate beneath the epitaxial silicon.

13. The method of claim 1 wherein implanting ions into at least the first epitaxial semiconductor layer further comprises:

implanting oxygen-containing ions with a concentration profile partially in the first epitaxial semiconductor layer and partially in the substrate beneath the epitaxial silicon.

14. A method of making a semiconductor structure, the method comprising:

etching a first trench in a mask on a substrate;

forming a semiconductor fin in the first trench, the semiconductor fin having a channel region;

forming an isolation region between the semiconductor fin and the substrate after partially forming the semiconductor fin;

forming a gate structure intersecting the channel region of the semiconductor fin; and

supporting the semiconductor fin with the mask while forming the gate structure.

15. The method of claim 14 wherein forming the semiconductor fin further comprises:

forming a first epitaxial layer of a semiconductor material in the first trench.

16. The method of claim 15 wherein forming the isolation region further comprises:

implanting ions into the first epitaxial layer exposed by the first trench and into a portion of the substrate underlying the first epitaxial layer; and

transforming the implanted ions into the buried isolation region electrically isolating the first epitaxial layer from the substrate.

17. The method of claim 16 wherein forming the semiconductor fin further comprises:

forming a second epitaxial layer of the semiconductor material in the first trench and on the first epitaxial layer to define the semiconductor fin.

18. The method of claim 16 wherein the semiconductor fin and the substrate include silicon, and the buried isolation region includes oxygen and silicon, and implanting the ions into the first epitaxial layer further comprises:

implanting oxygen-containing ions into the first epitaxial layer.

19. The method of claim 16 wherein an interface is defined between the epitaxial layer and the substrate, and implanting the ions into the first epitaxial layer further comprises:

selecting an ion energy such that an ion range of the implanted ions is near the interface.

20. The method of claim 16 wherein transforming the implanted ions into the buried isolation region further comprises:

performing a heat treatment to transform the implanted ions in the first epitaxial layer and the substrate into the buried isolation region.

21. The method of claim 20 wherein the thermal heat treatment anneals damage in the first epitaxial layer resulting from the ion implantation, and further comprising:

using the first epitaxial layer as a seed for forming a second epitaxial layer in the trench and on the first epitaxial layer.

22. The method of claim 15 wherein the substrate is monocrystalline and the trench extends to the substrate, and forming the first epitaxial layer further comprises:

using the substrate as a monocrystalline seed for forming the first epitaxial layer.

23. The method of claim 22 wherein forming the second epitaxial layer further comprises:

using the first epitaxial layer as a seed for forming a second epitaxial layer in the trench and on the first epitaxial layer to define the semiconductor fin.