Semiconductor power device having a top-side drain using a sinker trench

• US 7,352,036 B2
• Filed: 07/28/2005
• Issued: 04/01/2008
• Est. Priority Date: 08/03/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Dolny, Gary M., Grebs, Thomas E.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US11/194,060
• Publication Number:
  US 20060030142A1
• Time in Patent Office: 978 Days
• Field of Search: 257330-333, 257/341, 257/401, 438135-138, 438/172, 438/243, 438268-270
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.

Claims

1. A semiconductor power device comprising:

a substrate of a first conductivity type;

an epitaxial layer of the first conductivity type over and in contact with the substrate;

a first trench extending into and terminating within the epitaxial layer;

a sinker trench extending from the top surface of the epitaxial layer through the epitaxial layer and terminating within the substrate, the sinker trench being laterally spaced from the first trench, the sinker trench being wider and extending deeper than the first trench, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material in the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.

2. The semiconductor power device of claim 1 further comprising:

a well region of a second conductivity type in the epitaxial layer;

source regions of the first conductivity type in the well region, the source regions flanking the first trench;

a gate dielectric layer lining at least the sidewalls of the first trench; and

a gate electrode at least partially filling the first trench,

wherein a gate electrode contact layer electrically contacting the gate electrode, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device.

3. The semiconductor power device of claim 1 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, and metallic compound.

4. The semiconductor power device of claim 1 wherein the insulator comprises one of oxide, silicon nitride, silicon oxynitride, multilayer of oxide and nitride, a low k insulating material, and a high k insulating material.

5. A semiconductor power device comprising:

a substrate of a first conductivity type;

an epitaxial layer of the first conductivity type over and in contact with the substrate;

a well region of a second conductivity type in the epitaxial layer;

a gate trench extending through the epitaxial layer and the well region and terminating within the substrate, the gate trench including a gate dielectric layer lining at least the sidewalls of the gate trench, and a gate electrode at least partially filling the gate trench;

source regions of the first conductivity type in the well region, the source regions flanking the gate trench; and

a sinker trench extending from the top surface of the epitaxial layer through the epitaxial layer and terminating within the substrate, the sinker trench being laterally spaced from the gate trench, the sinker trench being wider than the gate trench, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material in the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.

6. The semiconductor power device of claim 5 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, and metallic compound.

7. The semiconductor power device of claim 5 wherein the insulator includes one of oxide, silicon nitride, multilayer of oxide and nitride, silicon oxynitride, a low k insulating material, and a high k insulating material.