Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique

• US 7,352,247 B2
• Filed: 08/22/2007
• Issued: 04/01/2008
• Est. Priority Date: 12/02/2004
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Oh, Hyoung-Seok, Yu, Hyun-Kyu, Kim, Cheon-Soo, Park, Mun-Yang
• Primary Examiner(s): Choe; Henry
• Application Number:
  US11/843,042
• Publication Number:
  US 20070285175A1
• Time in Patent Office: 223 Days
• Field of Search: 330/98, 330/150, 330/302, 330/310, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2203/7206 the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

Claims

1. A power amplifier, comprising:

an amplifying block with N transistors connected in parallel to receive and amplify an input signal individually;

a switching block that forms a cascode configuration by being connected to the amplifying block in series and that N transistors serially connected to each transistor in the amplifying block are connected in parallel;

a dynamic bias transistor that is operated by a dynamic gate bias by being connected in series between the switching block and an output end, and that reamplifies and outputs a signal coming from the switching block to the output end; and

a voltage dividing block that includes first and second capacitors connected in series between the output end and an ground, and that allots output signals through the first and second capacitors and provides the dynamic gate bias to a gate of the dynamic bias transistor.

2. The power amplifier as recited in claim 1, wherein the N transistors in the switching block are independently operated by N control signals, thereby controlling an effective channel width and bias current for each output mode.

3. The power amplifier as recited in claim 1, wherein the first capacitor is connected between the output end and a gate of the dynamic bias transistor, and the second capacitor is connected between the gate of the dynamic bias transistor and the ground.

4. The power amplifier as recited in claim 1, wherein the dynamic gate bias is determined based on a capacitance ratio of the first and second capacitors.

5. The power amplifier as recited in claim 1, further including:

an input matching circuit network which is for impedance matching of the input signal and connected between an input end that an input signal is received and the gate of the N transistors in the amplifying block.

6. The power amplifier as recited in claim 1, further including:

an output matching circuit network which is for impedance matching of the output signal and connected between an output end i.e. a drain node of a dynamic bias transistor, and an external load.

7. The power amplifier as recited in claim 1, wherein each of the N transistors in the amplifying block separately includes a common source transistor.

8. The power amplifier as recited in claim 1, wherein each of the N transistors in the switching block includes a common gate transistor.

9. The power amplifier as recited in claim 1, wherein a channel width of the N transistors in the amplifying block and the switching block is 2⁰W to 2^(N−

1)W.

10. The power amplifier as recited in claim 9, wherein the DC bias has 2^N−

1 different steps according to operation of the switching block.

11. The power amplifier as recited in claim 1, wherein an output matching circuit network connected for impedance matching of the output signal between an output end and an external load is further included, wherein the output matching circuit network varies impedance, which is seen from the output end, i.e. a drain node, of the dynamic bias transistor, according to the amplitude of the bias current flowing on the dynamic bias transistor.

12. The power amplifier as recited in claim 1, wherein power efficiency is optimized by selecting one bias current level among the usable DC bias levels through the operation of the switching block according to the amplitude of the input signal.

13. The power amplifier as recited in claim 1, wherein the N control signals are digital signals provided from a baseband Digital Signal Processing (DSP).

14. The power amplifier as recited in claim 1, wherein the dynamic bias transistor is connected to the DC supply voltage source through an inductor and DC bias voltage is provided from the DC supply voltage source to a gate through a resistor.

15. The power amplifier as recited in claim 1, further comprising:

a detecting block for detecting input signals and outputting different control signals according to the amplitude of the input signals;

a voltage providing block for controlling the amplitude of the DC supply voltage according to the control signals of the detecting block and outputting the different DC supply voltage; and

first and second bias resistors for dividing the DC supply voltage provided from the voltage providing block according to a resistance ratio by being connected between the voltage providing block and the ground, and providing the divided DC bias voltage to each gate of the transistors in the dynamic bias transistor and the switching block.

16. The power amplifier as recited in claim 15, wherein the DC bias voltage inputted to each gate of the transistors in the dynamic bias transistor and the switching block is determined according to the DC supply voltage provided from the voltage providing block and a resistance ratio of the first and second bias resistors.

17. The power amplifier as recited in claim 16, further comprising:

a first gate resistor connected between the voltage providing block and the gate of the dynamic bias transistor;

a second gate resistor, one end of which is connected to a part where the first and second bias resistors are connected; and

N switching elements connecting the second gate resistor with each gate of the N transistors in the switching block.

18. The power amplifier as recited in claim 17, wherein the N switching elements, each of which is a 3-way switch, are connected to the second gate resistor at a first end, connected to a capacitor, which is connected between each gate of the N transistors in the switching block and the ground, at the second end, and connected to the ground at the third end.