Digital-to-analog converter circuit

• US 7,352,314 B2
• Filed: 08/15/2006
• Issued: 04/01/2008
• Est. Priority Date: 08/16/2005
• Status: Expired due to Fees

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Epson Imaging Devices Corporation (Seiko Group)
• Inventors: Horibata, Hiroyuki
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US11/504,141
• Publication Number:
  US 20070052568A1
• Time in Patent Office: 595 Days
• Field of Search: 341/144, 341/150, 341/172, 341/153
• US Class Current: 341/150
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Data of a zero^th bit is supplied via a charge control transistor for the zero^th bit to a corresponding capacitor, data of a first bit is supplied via a charge control transistor for the first bit to a corresponding capacitor, and data of a second bit is supplied via a charge control transistor for the second bit to a corresponding capacitor. The capacitors for the zero^th bit, first bit, and second bit have capacitances which are set in a ratio of 1:2:4 and capabilities of the corresponding charge control transistors for respective bits are set in a ratio of 1:2:4. With this structure, charging of capacitors corresponding to the bits can be performed under similar conditions.

Claims

1. A digital-to-analog converter circuit comprising:

a plurality of capacitors each provided corresponding to each bit of digital data and having different capacitances from each other which are determined based on weights of the corresponding bits;

an output unit which outputs an analog voltage determined based on an amount of charge which is a total of charges charged to the plurality of capacitors and a total capacitance of the plurality of capacitors; and

a charge control transistor which is provided on a route of the digital data to each of the plurality of capacitors and controls supply of a voltage for each bit to the capacitor, wherein the transistor size of the charge control transistor is set corresponding to the capacitance of the capacitor to which the charge control transistor is connected such that the size of the charge control transistor is larger if the capacitor is larger.

2. A digital-to-analog converter circuit comprising:

a plurality of capacitors each provided corresponding to each bit of digital data and having different capacitances from each other which are determined based on weights of the corresponding bits;

an output unit which outputs an analog voltage determined based on an amount of charge which is a total of charges charged to the plurality of capacitors and a total capacitance of the plurality of capacitors; and

a charge control transistor which is provided on a route of the digital data to each of the plurality of capacitors and controls supply of a voltage for each bit to the capacitor, wherein the transistor size of the charge control transistor is set corresponding to the capacitance of the capacitor to which the charge control transistor is connected, wherein the plurality of capacitors each has a first terminal connected to a corresponding charge control transistor and have second terminals commonly connected to a power supply, and the output unit short-circuits a side of the first terminals of the plurality of capacitors and outputs the analog voltage from the first terminals.

3. A digital-to-analog converter circuit comprising:

a plurality of capacitors each provided corresponding to each bit of digital data and having different capacitances from each other which are determined based on weights of the corresponding bits;

an output unit which outputs an analog voltage determined based on an amount of charge which is a total of charges charged to the plurality of capacitors and a total capacitance of the plurality of capacitors; and

a charge control transistor which is provided on a route of the digital data to each of the plurality of capacitors and controls supply of a voltage for each bit to the capacitor, wherein the transistor size of the charge control transistor is set corresponding to the capacitance of the capacitor to which the charge control transistor is connected, wherein the plurality of capacitors each has a first terminal connected to a corresponding charge control transistor, and the output unit sets an identical voltage between both terminals of the plurality of capacitors and then switches the charge control transistor ON so that the analog voltage is output from the second terminals of the plurality of capacitors.