Vertical capacitor apparatus, systems, and methods

• US 7,352,557 B2
• Filed: 03/17/2005
• Issued: 04/01/2008
• Est. Priority Date: 09/24/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Han, Dong-Ho, He, Jiangqi, Kim, Joong-Ho, Kim, Hyunjun
• Primary Examiner(s): Ha; Nguyen T.
• Application Number:
  US11/082,341
• Publication Number:
  US 20050164465A1
• Time in Patent Office: 1,111 Days
• Field of Search: 361/306.3, 361/306.1, 361302-305, 361/321.1, 361/321.2, 257/528, 257/532, 257295-296
• US Class Current: 361/321.1
• CPC Class Codes: H01G 2/06 specially adapted for mounting on a printed-circuit support
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Claims

1. A method, comprising:

constructing a capacitor by forming a dielectric body between a first vertically-oriented plate having a first terminal coupled to a first bottom side and a second vertically-oriented plate having a second terminal coupled to a second bottom side, wherein the capacitor has terminals along only the bottom side;

forming a plurality of first vertically-oriented plates to couple to the first terminal;

coupling the plurality of first vertically-oriented plates to the first terminal;

forming a plurality of second vertically-oriented plates to couple to the second terminal; and

coupling the plurality of second vertically-oriented plates to the second terminal; and

wherein the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates have a height in the vertical direction that is greater than a horizontal thickness of the capacitor including a combined thickness of the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates.

2. The method of claim 1, wherein the first vertically-oriented plate and the second vertically-oriented plate comprise nickel.

3. The method of claim 1, wherein the dielectric body comprises a ceramic material.

4. The method of claim 1, wherein the capacitor further comprises a plurality of dielectric bodies, wherein the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates are spaced apart and adjacent at least one of the plurality of dielectric bodies, and wherein a vertical surface area of one of the plurality of first vertically-oriented plates is more than twice as large as a bottom surface area of a package housing the plurality of first vertically-oriented plates, the plurality of second vertically-oriented plates, and the plurality of dielectric bodies.

5. A method, comprising:

operating a field programmable gate array coupled to a capacitor having a dielectric body disposed between a first vertically-oriented plate having a first terminal coupled to a first bottom side and a second vertically-oriented plate having a second terminal coupled to a second bottom side, wherein the capacitor has terminals along only the bottom side;

wherein the capacitor further comprises

a plurality of first vertically-oriented plates coupled to the first terminal; and

a plurality of second vertically-oriented plates coupled to the second terminal; and

wherein the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates have a height in the vertical direction that is greater than a horizontal thickness of the capacitor including a combined thickness of the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates.

6. The method of claim 5, wherein operating the field programmable gate array further comprises:

executing a plurality of Boolean logic instructions.

7. The method of claim 5, further comprising:

operating a transceiver coupled to the field programmable gate array.

8. The method of claim 5, wherein a circuit board having a planar surface oriented in a substantially horizontal fashion is coupled to the capacitor, and wherein the at least one first vertically-oriented plate and the at least one second vertically-oriented plate are oriented in a substantially vertical fashion with respect to the planar surface.

9. The method of claim 5, wherein the capacitor further comprises a plurality of dielectric bodies, wherein the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates are spaced apart and adjacent at least one of the plurality of dielectric bodies, and wherein a vertical surface area of one of the plurality of first vertically-oriented plates is more than twice as large as a bottom surface area of a package housing the plurality of first vertically-oriented plates, the plurality of second vertically-oriented plates, and the plurality of dielectric bodies.

10. A method, comprising:

operating a transceiver coupled to a capacitor having a dielectric body disposed between a first vertically-oriented plate having a first terminal coupled to a first bottom side and a second vertically-oriented plate having a second terminal coupled to a second bottom side, wherein the capacitor has terminals along only the bottom side;

wherein the capacitor further comprises

a plurality of first vertically-oriented plates coupled to the first terminal; and

a plurality of second vertically-oriented plates coupled to the second terminal; and

wherein the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates have a height in the vertical direction that is greater than a horizontal thickness of the capacitor including a combined thickness of the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates.

11. The method of claim 10, wherein the transceiver forms a portion of a cellular telephone.

12. The method of claim 10, wherein a circuit board having a planar surface oriented in a substantially horizontal fashion is coupled to the capacitor, and wherein the at least one first vertically-oriented plate and the at least one second vertically-oriented plate are oriented in a substantially vertical fashion with respect to the planar surface.

13. The method of claim 10, wherein the transceiver is coupled to an omni-directional antenna.

14. The method of claim 10, wherein the capacitor further comprises a plurality of dielectric bodies, wherein the plurality of first vertically-oriented plates and the plurality of second vertically-oriented plates are spaced apart and adjacent at least one of the plurality of dielectric bodies, and wherein a vertical surface area of one of the plurality of first vertically-oriented plates is more than twice as large as a bottom surface area of a package housing the plurality of first vertically-oriented plates, the plurality of second vertically-oriented plates, and the plurality of dielectric bodies.