Method for enhanced block management

• US 7,352,621 B2
• Filed: 06/23/2005
• Issued: 04/01/2008
• Est. Priority Date: 06/23/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Rothman, Michael A.
• Primary Examiner(s): Pham; Lý Duy
• Application Number:
  US11/166,842
• Publication Number:
  US 20060291304A1
• Time in Patent Office: 1,013 Days
• Field of Search: 365/185.09, 365/200, 711/200, 711/201, 711/202, 711/204, 711/205, 711/206, 711/213
• US Class Current: 365/185.09
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block is remapped to a spare block, if the block is predicted as a bad block. Remapping is done for blocks used to store code both in serial execution code sequences and code sequences utilizing address translation. The remapping of bad blocks/sectors in nonvolatile memory allows nonvolatile memory in computer systems to be robust and resilient in handling bad blocks.

Claims

1. An apparatus comprising:

a nonvolatile memory erasable in blocks including,

a preceding block to store code;

a target block to store code; and

a replacement block to store code; and

logic to insert preceding pad bits in the preceding block to remap the target block to the replacement block, in response to the target block being identified as a bad block,

wherein the target block is identified as a bad block if accessing the target block results in N I/O faults, N being any positive integer.

2. The apparatus of claim 1, wherein the nonvolatile memory is a FLASH device to store basic input/output software (BIOS) code.

3. The apparatus of claim 1, wherein the preceding pad bits represent a jump command to jump around the target block to the replacement block.

4. The apparatus of claim 1, wherein the preceding pad bits represent a reference to the replacement block.

5. The apparatus of claim 4, wherein the nonvolatile memory further includes a subsequent block, wherein the logic is also to insert replacement pad bits in the replacement block, the replacement pad bits to represent a reference to the subsequent block.

6. The apparatus of claim 5, wherein the logic comprises firmware to insert the preceding pad bits in a pad field of the preceding block and the replacement pad bits in a pad field of the replacement block, and wherein the reference to the replacement block includes a jump command to the replacement block and the reference to the subsequent block includes a jump command to the subsequent block.

7. The apparatus of claim 5, wherein the preceding block precedes and is contiguous with the target block, and wherein the subsequent block succeeds and is contiguous with the target block.

8. The apparatus of claim 6, wherein the nonvolatile memory is to store code serially in the plurality of blocks for execution in an execute in place (XiP) architecture.

9. A system comprising:

a flash memory including,

a predicted bad block of a plurality of blocks, and

logic to insert a first reference to a replacement block in a first pad field of a preceding block, which precedes the predicted bad block, and insert a second reference to a subsequent block, which succeeds the predicted bad block, in a second pad field of the replacement block; and

a processing element to execute code stored in the replacement block instead of the predicted bad block in response to the first reference to the replacement block in the first pad field of the preceding block.

10. The system of claim 9, wherein the predicted bad block is to be determined as a predicted bad block in response to an a failed access to the predicted bad block by the processing element.

11. The system of claim 9, wherein the processing element is selected from a group consisting of an embedded controller, a microcontroller, a controller hub, a microprocessor, a co-processor, a digital signal processor, a processing cell, and an an out-of-order microprocessor capable of executing multiple threads in parallel.

12. The system of claim 9, wherein the processing element executes the plurality of blocks in the flash memory in-place.

13. A method comprising:

detecting an I/O fault, upon an access to a target sector of a nonvolatile memory;

determining if the target sector is predicted as a bad sector; and

inserting a jump instruction in a pad field of a first sector immediately preceding the target sector to jump execution over the target sector to a replacement sector, which immediately follows the target sector, in response to determining the target sector is predicted as a bad sector,

wherein the target sector is determined to be predicted as a bad sector in response to a predefined number of I/O faults to the target sector.

15. The method of claim 13, wherein patching a pad field of the preceding sector to point to the spare sector comprises inserting a first jump instruction in the pad field of the preceding sector to jump execution from the preceding sector to the spare sector, and wherein patching a pad field of the spare sector to point to the continuation sector comprises inserting a second jump instruction in the pad field of the spare sector to jump execution from the spare sector to the continuation sector.

14. A method comprising,

detecting a bad sector of a nonvolatile memory, the nonvolatile memory including a preceding sector prior to the bad sector, a continuation sector subsequent to the bad sector, and a spare sector, wherein the preceding sector, the bad sector, and the continuation sector are to store code in an execute in place (XiP) code sequence;

and

in response to detecting the bad sector migrating data stored in the bad sector to spare sector;

patching a pad field of the preceding sector to point to the spare sector; and

patching a pad field of the spare sector to point to the continuation sector.

16. The method of claim 14, wherein the nonvolatile memory is a memory device selected from a group consisting of a flash device, an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a programmable logic array (PLA), and a random access memory (RAM) with a battery backup.