Voltage regulator with less overshoot and faster settling time

• US 7,352,626 B1
• Filed: 08/29/2005
• Issued: 04/01/2008
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Wu, Yonggang, Wang, Guowei, Yang, Nian, Lee, Aaron
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/212,614
• Time in Patent Office: 946 Days
• Field of Search: 365/185.01, 365/185.18, 365/185.21, 365/185.23, 365/185.25, 365/185.33, 365/207, 365/203, 365/205, 365/208, 365/226
• US Class Current: 365/185.18
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.

Claims

1. A memory device comprising:

at least one array of non-volatile memory cells, each of the non-volatile memory cells being associated with at least one bit line and a word line; and

a voltage supply component configured to supply power to the at least one array of non-volatile memory cells, the voltage supply component including a voltage regulator that includes;

an operational-amplifier section,

a capacitor connected to an output of the operational-amplifier section, and

a switch configured to connect the capacitor and the output of the operational-amplifier section to a voltage supply, the switch being operated to pre-charge the capacitor, the pre-charged capacitor operating to stabilize the power supplied from the voltage supply component.

2. The memory device of claim 1, wherein the voltage regulator further includes:

a second switch connected between first and second stages of the two-stage operational-amplifier, the second switch being configured to be in a non-conductive state while the capacitor is pre-charging.

3. The memory device of claim 2, further comprising:

a resistor connected in parallel with the capacitor.

4. The memory device of claim 1, wherein the operational amplifier section includes:

a first operational-amplifier configured as a differential operational-amplifier; and

a second operational-amplifier connected at an input to an output of the first operational-amplifier and being configured as a unity gain operational amplifier.

5. The memory device of claim 4, wherein the operational amplifier section further includes:

a second switch connected between the first and second operational-amplifiers, the second switch being configured to be in a non-conductive state while the capacitor is pre-charging.

6. The memory device of claim 5, wherein the operational amplifier section further includes:

a second capacitor connected between the output of the operational-amplifier and the input of the second operational amplifier.

7. The memory device of claim 5, further comprising:

control logic configured to control operation of the first and second switches.

8. The memory device of claim 1, wherein the voltage supply component further includes:

a charge pump component configured to output a supply voltage to the voltage regulator.

9. The memory device of claim 1, wherein each of the non-volatile memory cells includes:

a dielectric charge storage element configured to store at least two independent charges.

10. The memory device of claim 1, wherein the non-volatile memory cells are SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cells.

11. A non-volatile memory device comprising:

an array of non-volatile memory cells, each of the non-volatile memory cells being associated with at least one bit line and a word line; and

a voltage regulator that includes;

a two-stage operational-amplifier section, the two-stage operational-amplifier section including a first operational-amplifier configured as a differential operational-amplifier, and a second operational-amplifier configured as a unity gain operational amplifier and including an input connected to an output of the first operation-amplifier and an output connected as an output of the two-stage operational-amplifier section,

a capacitor connected to an output of the two-stage operational-amplifier section, and

a switch configured to connect the capacitor and the output of the two-stage operational-amplifier section to a voltage supply, the switch being operated to charge the capacitor before activating the two-stage operational-amplifier section.

12. The non-volatile memory device of claim 11, wherein the voltage regulator further includes:

a second switch connected between the first and second operational-amplifiers, the second switch being configured to be in a non-conductive state while the capacitor is charging.

13. The non-volatile memory device of claim 11, wherein the array of non-volatile memory cells includes NOR-type Flash memory cells.

14. The non-volatile memory device of claim 11, wherein the capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section.