Method, system, and circuit for operating a non-volatile memory array

• US 7,352,627 B2
• Filed: 01/03/2006
• Issued: 04/01/2008
• Est. Priority Date: 01/03/2006
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Cohen, Guy
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/324,718
• Publication Number:
  US 20070153575A1
• Time in Patent Office: 819 Days
• Field of Search: 365/185.2, 365/185.03, 365/201, 365/210, 365/189.09
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset value may be determined for a memory cell to be operated based on a location (e.g. memory segment within a memory array) of the memory cell. An input offset circuit of a global reference cell may be adjusted by the threshold offset value for the memory cell; and the memory cell may be operated (e.g. read, written or erased) using the global reference cell whose input offset circuit has been adjusted by the threshold offset value. According to some embodiments of the present invention global reference cells may consist of multiple sets of reference cells, wherein, according to some aspects, each set of the multiple sets of reference cells may be used for operating a different memory array segment. According to other aspects, each set of the multiple sets of reference cells may be used for operating a different state of memory array cells.

Claims

1. A method of operating a memory cell in a memory array segment, said method comprising:

determining a threshold offset value for said memory array segment by accessing a table offset values associated with said segment; and

adjusting an input offset circuit of global reference cells by the threshold offset value defined for said memory cell.

2. The method according to claim 1, wherein a reference cell is selected from the global reference cells based on an offset value defined in the offset table for the memory cell.

3. The method according to claim 1, further comprising measuring an offset value for each of a set of memory array segments.

4. The method according to claim 2, further comprising programming said offset table with the measured offset values.

5. The method according to claim 1, wherein the step of adjusting an offset circuit comprises forwarding to the offset circuit a signal correlated with on offset value.

6. The method according to claim 1, wherein the global reference cells comprise multiple sets of reference cells.

7. The method according to claim 6, wherein each set of the multiple sets of reference cells is used for operating a different memory array segment.

8. The method according to claim 6, wherein each set of the multiple sets of reference cells is used far operating a different state of memory array segments.

9. A method of operating a memory cell in a memory array, comprising:

determining a threshold offset value based on a location of said memory cell and on the operation to be performed and by accessing a table offset values associated with said segment;

adjusting an input offset circuit of global reference cells by the threshold offset value for said memory cell; and

operating said cell by using the global reference cells whose input offset circuit has been adjusted.

10. The method according to claim 9, wherein the step of determining a threshold offset value is comprised of accessing a table of offset values for a set of memory array segments and looking up a threshold offset value associated with the memory segment in which said memory cell resides.

11. The method according to claim 9, further comprising measuring an offset value for each of a set of memory array segments.

12. The method according to claim 10, further comprising storing in said offset table data relating to the measured offset values.

13. The method according to claim 12, wherein storing comprises programming a non volatile segment of the memory array with the measured offset values.

14. The method according to claim 9, wherein the step of adjusting an offset circuit comprises forwarding to an offset circuit a signal correlated to an offset value.

15. A memory array circuit comprising:

an offset table comprising at least two offset values, wherein each offset value is associated with at least one memory segment in said memory array and is determined by accessing a table of offset values associated with said segment; and

an adjustable reference cell circuit comprising global reference cells having a substantially fixed threshold and an input offset circuit to adjust by an offset value of a voltage applied to said global reference cells.

16. The memory array circuit according to claim 15, wherein the global reference cells comprise multiple sets of reference cells.

17. The memory array circuit according to claim 16, wherein each set of the multiple sets of reference cells is used for operating a different memory array segment.

18. The memory array circuit according to claim 16, wherein each set of the multiple sets of reference cells is used for operating a different state of memory array segments.