Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices

• US 7,353,007 B2
• Filed: 02/03/2005
• Issued: 04/01/2008
• Est. Priority Date: 02/03/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Carballo, Juan-Antonio, Nowka, Kevin John, Vo, Ivan, Yoo, Seung-moon
• Primary Examiner(s): Vo; Nguyen T.
• Assistant Examiner(s): Le; Nhan T.
• Application Number:
  US11/050,019
• Publication Number:
  US 20060172715A1
• Time in Patent Office: 1,153 Days
• Field of Search: 455/127.1, 455/127.2, 455/127.5, 455/550.1, 455/552.1, 375/297, 375/275, 375/295, 330/51, 330/207, 330/251, 330/207.R, 330/302
• US Class Current: 455/127.2
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Claims

1. A transmission circuit for transmitting a digital signal to one or more interface conductors, comprising:

a plurality of parallel driver slices each comprising a plurality of cascaded driver stages, wherein said slices have common output nodes at each stage, whereby drive currents of said stages are generated as the sum of unequal individual drive currents of each slice at each particular stage; and

a control logic for selectively enabling said parallel driver slices, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level, wherein said individual drive currents of each slice at each particular stage are weighted to different values to provide a range of selectable drive levels exceeding N;

1, where N is the number of said driver slices.

2. The transmission circuit of claim 1, wherein said individual drive currents at each slice at each particular stage are weighted by powers of two, whereby a binary selection of transmitter current is provided.

3. The transmission circuit of claim 1, wherein said individual drive currents at each slice at each particular stage are weighted by arbitrary factors, whereby a selection of transmitter current is provided in accordance with a discrete set of transmitter power requirements.

4. The transmission circuit of claim 1, wherein each of said slices comprises a plurality of inverters connected in series and wherein at least two of said inverters have power supply connections connected to at least one common virtual supply rail and wherein said transmission circuit further comprises at least one power supply control transistor having a control input coupled to said control logic, whereby said at least two inverters are enabled and disabled.

5. The transmission circuit of claim 1, wherein each of said slices comprises a plurality of buffers connected in series and wherein at least two of said buffers have power supply connections connected to at least one common virtual supply rail and wherein said transmission circuit further comprises at least one power supply control transistor having a control input coupled to said control logic, whereby said at least two buffers are enabled and disabled.

6. The transmission circuit of claim 1, further comprising a decoder for receiving a plurality of select signals and generating an enable signal for each slice.

7. The transmission circuit of claim 6, further comprising a programmable register for receiving a value corresponding to a transmitter signal level and holding said value, and wherein outputs of said programmable register are coupled to said decoder for providing said plurality of select signals.

8. The transmission circuit of claim 1, wherein each of said slices comprises a plurality of inverters connected in series and each further comprise at least one power supply control transistor having a control input coupled to said control logic, whereby said inverters are enabled and disabled, and wherein said at least one power supply control device has a threshold voltage greater than that of transistors forming said inverters.

9. The transmission circuit of claim 1, wherein each of said slices comprises a plurality of buffers connected in series and each further comprise at least one power supply control transistor having a control input coupled to said control logic, whereby said buffers are enabled and disabled, and wherein said at least one power supply control device has a threshold voltage greater than that of transistors forming said buffers.

10. An interface including:

a transmission circuit for transmitting a digital signal to one or more interface conductors, comprising

an output driver having a plurality of parallel driver slices each comprising a plurality of cascaded driver stages, wherein said slices have common output nodes at each stage, whereby a drive current at each stage is generated as the sum of unequal individual drive currents of each slice at each stage and a control logic for selectively enabling said parallel driver slices in response to one or more control signals, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level; and

an interface quality measurement circuit for providing said one or more control signals in response to a determination of quality of signals on said interface conductors, wherein said individual drive currents of each slice at each particular stage are weighted to different values to provide a range of selectable drive levels exceeding N;

1, where N is the number of said driver slices.

11. The interface of claim 10, wherein said interface quality measurement circuit is located on a remote side of said interface conductors opposite said output driver, and further comprising:

a second transmission circuit located on said remote side of said interface and coupled to said interface conductors and said interface quality measurement circuit for transmitting indications of said signal quality determination;

a receiver on a local side of said interface and coupled to said one or more interface conductors for receiving said indications from said remote side of said interface and for providing said one or more control signals in response to said received indications.

12. The interface of claim 10, wherein said interface quality measurement circuit is located on a local side of said interface conductors along with said output driver, and wherein said interface quality measurement circuit is coupled to said control circuit for providing said one or more control signals.

13. A transmission circuit for transmitting a digital signal to one or more interface conductors, comprising:

a plurality of parallel driver slices each comprising a plurality of cascaded driver stages, wherein said slices have common output nodes at each stage, whereby drive currents of said stages are generated as the sum of unequal individual drive currents of each slice at each particular stage; and

a control logic for selectively enabling said parallel driver slices, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level;

a decoder for receiving a plurality of select signals and generating an enable signal for each slice; and

a programmable register for receiving a value corresponding to a transmitter signal level and holding said value, and wherein outputs of said programmable register are coupled to said decoder for providing said plurality of select signals.