Circuit simulation

• US 7,353,157 B2
• Filed: 01/11/2002
• Issued: 04/01/2008
• Est. Priority Date: 01/11/2001
• Status: Expired due to Term

• Current Assignee: PC Krause & Associates, Inc.
• Original Assignee: PC Krause & Associates, Inc.
• Inventors: Jatskevich, Juri V., Wasynczuk, Oleg
• Primary Examiner(s): Shah; Kamini
• Assistant Examiner(s): Silver; David
• Application Number:
  US10/043,981
• Publication Number:
  US 20020183990A1
• Time in Patent Office: 2,272 Days
• Field of Search: 703/14, 703/13, 716/18
• US Class Current: 703/14
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A system, method, and apparatus select state variables for, build state equations of, and simulate time-domain operation of an electronic circuit. The circuit is modeled with three branch types (inductor, resistor, voltage source in series; capacitor, resistor, current source in parallel; and switch), including four pre-defined switch types (unidirectional unlatched, bidirectional unlatched, unidirectional latched, and bidirectional latched). Automated analyses determine efficient state variables based on the currently active circuit topology, and state equations are built and applied. Switching logic determines when switch states change, and state equations for the new topology are either drawn from a cache (if the topology has already been processed) or derived anew. The switch control signals may be combined into a single switching variable, defined as a function of the state output.

Claims

1. A computer-implemented method, comprising:

creating one or more data structures that together store characteristics of a plurality of active branches B^active that make up a graph of nodes and branches that form a circuit, wherein B^active consists of

a set B^L of zero or more inductive branches, each having a non-zero inductive component but neither a capacitive component nor a variable switch state;

a set B^C of zero or more capacitive branches, each having a non-zero capacitive component but neither an inductive component nor a variable switch state; and

a set B^A of additional branches, each having neither an inductive component, nor a capacitive component;

partitioning B^active into a first branch set B_tree^active and a second branch set B_link^active, where the branches in B_tree^active form a spanning tree over B^active, giving priority in said partitioning to branches not in B^L over branches in B^L;

sub-partitioning B_link^active into a third branch set B_link^L and a fourth branch set B_link^CA, where B_link^L=B_link^active∩

B^L;

identifying a fifth branch set B^CA as the union of

B_link^CA,

B^C∩

B_tree^active, and

those branches in B_tree^active that form a closed graph when combined with B_link^CA;

partitioning B^CA into a sixth branch set {tilde over (B)}_tree^CA and a seventh branch set {tilde over (B)}_link^CA, where the branches in {tilde over (B)}_tree^CA form a spanning tree over B^CA, giving priority in said partitioning to branches in B^C over branches not in B^C;

identifying an eight branch set B_tree^C={tilde over (B)}_tree^CA∩

B^C;

selecting a set of state variables comprising;

for each branch of B_link^L, either the inductor current or inductor flux, and

for each branch of B_tree^C, either the capacitor voltage or capacitor charge; and

simulating a plurality of states of the circuit using the set of state variables.

2. The method of claim 1, wherein said partitioning steps each comprise an application of a weighted spanning tree algorithm.

3. The method of claim 2 wherein, for some positive numbers w_L and w_C:

for the partitioning of B^active, a minimum spanning true algorithm is used with weight function

4. A system, comprising a processor and a computer-readable medium in communication with said processor, said medium containing programming instructions executable by said processor to:

build state equations for a first topology of an electronic circuit having at least two switching elements, wherein each switching element has a switching state;

solve said state equations at time t_t to provide a state output vector, in which at least two elements control the switching states of tlie switching elements;

calculate the value of a switching variable as a function of the state output vector, wherein the value reflects whether the switching state of at least one of the switching elements is changing; and

if the value of the switching variable at time t_t indicates that at least one of the switching elements is changing, determine a second topology of the electronic circuit for time t_i⁺ and obtain state equations forte second topology;

wherein;

said programming instructions comprise a state equation building module, a solver module for ordinary differential equations, and a switching logic module;

said building is performed by the state equation building module;

said solving and calculating are performed by the solver module;

said determining is performed by the switching logic module;

at a time t_j, at least two switching elements are each either rising-sensitive or falling-sensitive switches, wherein

rising-sensitive switches change switching state if and only if a controlling element of the state vector has passed from a negative value to a non-negative value; and

falling-sensitive switches change switching state if and only if a controlling element of the state vector has passed from a positive value to a non-positive value; and

the function is the arithmetic maximum of

a maximum of all controlling elements of the state vector that control rising-sensitive switches, and

the negative of the minimum of all controlling elements of the state vector that control falling-sensitive switches.