General input/output architecture, protocol and related methods to manage data integrity

• US 7,353,313 B2
• Filed: 10/23/2006
• Issued: 04/01/2008
• Est. Priority Date: 08/24/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Moore, Wayne, Wehage, Eric R., Creta, Ken, Gremel, Buck, Fanning, Blaise, Ajanovic, Jasmin, Harriman, David, Lee, David M.
• Primary Examiner(s): Myers; Paul R.
• Application Number:
  US11/585,648
• Publication Number:
  US 20070038793A1
• Time in Patent Office: 526 Days
• Field of Search: 710/305, 710/100, 714/4, 714/758, 714/746
• US Class Current: 710/305
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4252 using a handshaking protocol
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes

Abstract

An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g., implemented within a bridge), a switch, and end-points, each incorporating at least a subset of EGIO features to support EGIO communication between such elements.

Claims

1. A method comprising:

receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link;

validating content of one or more packets embedded within the received datagram by determining whether the one or more packets meet predetermined framing requirements;

if the framing requirements are met, stripping framing boundaries from the datagram to reveal one or more data link layer packets; and

issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded data link layer packets to a transaction layer of the GIO interface, wherein the acknowledgement includes flow control update information to be transmitted to the GIO interface.

2. A method according to claim 1, the element of validating comprising:

confirming that the datagram was received at a physical link layer of the GIO interface from the GIO link without error.

3. A method according to claim 2, the element of validating further comprising:

identifying a sequence number associated with the received datagram; and

confirming that an accurate sequence number is associated with the received datagram based, at least in part, on a last sequence number employed in communication between the interface(s).

4. A method according to claim 3, the element of validating further comprising:

identifying an indication of content integrity within the received datagram;

independently calculating an indication of content integrity based, at least in part, on the content of the datagram; and

confirming that the identified indication matches that of the calculated indication.

5. A method according to claim 4, wherein the indication of content integrity is a cyclical redundancy check (CRC) value.

6. A method according to claim 2, the element of validating further comprising:

identifying an indication of content integrity within the received datagram;

independently calculating an indication of content integrity based, at least in part, on the content of the received datagram; and

confirming that the identified indication matches that of the calculated indication.

7. A method according to claim 6, wherein the indication of content integrity is a hash of at least a subset of content of the datagram.

8. A method according to claim 1, the element of validating comprising:

identifying an indication of payload integrity within the received datagram;

independently calculating the indication of payload integrity based, at least in part, on the payload of the datagram; and

confirming that the identified indication matches that of the calculated indication.

9. A method according to claim 1, the element of validating comprising:

identifying a sequence number associated with the received datagram; and

confirming that an accurate sequence number is associated with the received datagram based, at least in part, on a last sequence number employed in communication between the interface(s).

10. A method according to claim 1, the element of issuing an acknowledgement comprising:

issuing a positive acknowledgement if the datagram is validated.

11. A method according to claim 1, the element of issuing an acknowledgement comprising:

issuing a negative acknowledgement if the datagram fails to validation.

12. A method according to claim 11, the element of issuing a negative acknowledgement further comprising:

maintaining a count of successive negative acknowledgements; and

reinitialize the GIO link between the GIO interface and the remote GIO interface.

13. A method according to claim 1, further comprising:

promoting a validated packet to a transaction layer of the GIO interface.

14. A general input/output (GIO) interface comprising:

a physical layer, to couple the GIO interface to a GIO communication link; and

a data link layer, coupled with the physical layer, to

receive a datagram from a remote GIO interface through the GIO communication link, wherein the GIO interface is implemented on a communication port implementing a communication stack including a data link layer,

validate content of one or more packets embedded within the received datagram by determining whether the one or more packets meet predetermined framing requirements,

if the framing requirements are met, strip framing boundaries from the datagram to reveal one or more data link layer packets, and

issue an acknowledgement to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded data link layer packets to a transaction layer of the GIO interface, wherein the acknowledgement includes flow control update information to be transmitted to the GIO interface.

15. A GIO interface according to claim 14, wherein the data link layer receives an indication from the physical layer that the datagram was received from the GIO link without error.

16. A GIO interface according to claim 15, wherein the data link layer identifies a sequence number associated with the received datagram, and confirms that an accurate sequence number is associated with the received datagram based, at least in part, on a last sequence number employed in communication between the interface(s) to validate the received datagram.

17. A GIO interface according to claim 16, wherein the data link layer identifies an indication of payload integrity within the received datagram, calculates another version of the indication based, at least in part, on the payload of the datagram, and confirms that the identified indication matches the calculated indication to validate content of the received datagram.

18. A GIO interface according to claim 17, wherein the data link layer promotes content of the received datagram to a coupled transaction layer of the GIO interface upon validation of the content of the received datagram.

19. A GIO interface according to claim 17, wherein the data link layer issues a negative acknowledgement if the content of the received datagram fails validation.

20. A GIO interface according to claim 19, wherein the data link layer initiates reinitialization of the communication link through the physical layer after issuing one or more negative acknowledgements.

21. A GIO interface according to claim 14, wherein the data link layer identifies an indication of payload integrity within the received datagram, calculates another version of the indication based, at least in part, on the payload of the datagram, and confirms that the identified indication matches the calculated indication to validate content of the received datagram.

22. A GIO interface according to claim 21, wherein the indication is a cyclical redundancy check (CRC) value.

23. An electronic component, suitable for use in an electronic device, comprising a GIO interface according to claim 14.

24. An electronic appliance comprising a plurality of electronic components according to claim 23.