Memory hub and method for memory sequencing

• US 7,353,320 B2
• Filed: 10/12/2006
• Issued: 04/01/2008
• Est. Priority Date: 05/14/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Verbrugge; Kevin
• Application Number:
  US11/580,424
• Publication Number:
  US 20070033353A1
• Time in Patent Office: 537 Days
• Field of Search: None
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory sequencer that adjusts its operation based on the system metrics tracked by the performance counter.

Claims

1. A memory module, comprising:

at least one memory device; and

a memory hub, comprising;

a link interface operable to receive memory requests for access to memory cells in the at least one memory device;

a memory device interface coupled to the at least one memory devices, the memory device interface being operable to couple memory requests to the at least one memory devices for access to memory cells in the at least one memory device and to receive read data responsive to at least some of the memory requests;

a performance determining device coupled to the memory device interface, the performance determining device operable to track at least one performance metric; and

a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance determining device.

2. The memory module of claim 1 wherein the link interface comprises an optical input/output port.

3. The memory module of claim 1 wherein the performance metric tracked by the performance determining device comprises at least one performance metric selected from the group consisting of page hit rate, prefetch hits, and cache hit rate.

4. The memory module of claim 3 wherein the performance determining device is operable to track page hit rate, and the memory sequencer is operable to change a number of open pages in the at least one memory device.

5. The memory module of claim 3 wherein the performance determining device is operable to track page hit rate, and the memory sequencer is operable to switch to auto-precharge mode.

6. The memory module of claim 3 wherein the performance determining device is operable to track a percentage of prefetch hits, and the memory sequencer is operable to enable prefetching or disable prefetching.

7. The memory module of claim 3 wherein the performance determining device is operable to track a percentage of prefetch hits, and the memory sequencer is operable to determine a number of prefetch requests.

8. The memory module of claim 3 wherein the performance determining device is operable to track a cache hit rate, and the memory sequencer is operable to disable the cache.

9. A memory hub, comprising:

a link interface receiving memory requests;

a memory device interface operable to transmit memory requests and to receive read data responsive to at least some of the memory requests;

a performance determining device coupled to the memory device interface, the performance determining device operable to track at least one performance metric; and

a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance determining device.

10. The memory hub of claim 9 wherein the performance metric tracked by the performance determining device comprises at least one performance metric selected from the group consisting of page hit rate, prefetch hits, and cache hit rate.

11. The memory hub of claim 10 wherein the performance determining device is operable to track page hit rate, and the memory sequencer is operable to change a number of open pages in the memory device.

12. The memory hub of claim 10 wherein the performance determining device is operable to track page hit rate, and the memory sequencer is operable to switch to auto-precharge mode.

13. The memory hub of claim 10 wherein the performance determining device is operable to track a percentage of prefetch hits, and the memory sequencer is operable to enable prefetching or disable prefetching.

14. The memory hub of claim 10 wherein the performance determining device is operable to track a percentage of prefetch hits, and the memory sequencer is operable to determine a number of prefetch requests.

15. The memory hub of claim 10 wherein the performance determining device is operable to track a cache hit rate, and the memory sequencer is operable to disable the cache.

16. A processor-based system, comprising:

a processor;

a controller coupled to the processor, the controller having an input port and an output port;

an input device coupled to the processor;

an output device coupled to the processor;

a storage device coupled to the processor;

a plurality of memory modules, each of the memory modules comprising;

at least one memory device; and

a memory hub, comprising;

a link interface operable to receive memory requests for access to memory cells in the at least one memory device;

a memory device interface coupled to the at least one memory device, the memory device interface being operable to couple memory requests to the at least one memory device for access to memory cells in the at least one memory device and to receive read data responsive to at least some of the memory requests;

a performance determining device coupled to the memory device interface, the performance counter operable to track at least one performance metric; and

a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance determining device.

17. The processor-based system of claim 16 wherein the performance metric tracked by the performance determining device comprises at least one performance metric selected from the group consisting of page hit rate, prefetch hits, and cache hit rate.

18. The processor-based system of claim 17 wherein the performance is operable to track page hit rate, and the memory sequencer is operable to change a number of open pages in the memory device.

19. The processor-based system of claim 17 wherein the performance determining device is operable to track page hit rate, and the memory sequencer is operable to switch to auto-precharge mode.

20. The processor-based system of claim 17 wherein the performance determining device is operable to track a percentage of prefetch hits, and the memory sequencer is operable to enable prefetching or disable prefetching.

21. The processor-based system of claim 17 wherein the performance determining device is operable to track a percentage of prefetch hits, and the memory sequencer is operable to determine a number of prefetch requests.

22. The processor-based system of claim 17 wherein the performance determining device is operable to track a cache hit rate, and the memory sequencer is operable to disable the cache.

23. A method of reading data from a memory module, comprising:

receiving memory requests for access to at least one memory device mounted on the memory module;

coupling the memory requests to the at least one memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data;

receiving read data responsive to at least some of the read memory requests;

tracking at least one performance metric of the memory module; and

adjusting operability of the memory module based on the tracked performance metric.

24. The method of claim 23 wherein the act of tracking at least one performance metric of the memory module comprises tracking at least one performance metric selected from the group consisting of page hit rate, prefetch hits, and cache hit rate.

25. The method of claim 23 wherein the act of adjusting operability of the memory module based on the tracked metric comprises adjusting operability of the memory module if the tracked metric exceeds a threshold level.

26. The method of claim 24 wherein the act of adjusting operability of the memory module based on the tracked metric comprises adjusting operability of the memory module if the tracked metric is less than a threshold level.

27. The method of claim 24 wherein the tracked performance metric comprises page hit rate, and the act of adjusting operability of the memory module based on the tracked performance metric comprises adjusting operability of the memory module to change a number of open pages in the at least one memory device.

28. The method of claim 24 wherein the tracked performance metric comprises page hit rate, and the act of adjusting operability of the memory module based on the tracked performance metric comprises adjusting operability of the memory module to switch to auto-precharge mode.

29. The method of claim 24 wherein the tracked performance metric comprises a percentage of prefetch hits, and the act of adjusting operability of the memory module based on the tracked performance metric comprises adjusting operability of the memory module to enable prefetching or disable prefetching.

30. The method of claim 24 wherein the tracked performance metric comprises a percentage of prefetch hits, and the act of adjusting operability of the memory module based on the tracked performance metric comprises adjusting operability of the memory module to adjust a number of prefetch requests.

31. The method of claim 24 wherein the tracked performance metric comprises a cache hit rate, and the act of adjusting operability of the memory module based on the tracked performance metric comprises adjusting operability of the memory module to disable the cache.