System and method for testing a memory for a memory failure exhibited by a failing memory

• US 7,353,437 B2
• Filed: 10/29/2004
• Issued: 04/01/2008
• Est. Priority Date: 10/29/2004
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Crump, Valerie, Van Roosendaal, Brad
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US10/977,391
• Publication Number:
  US 20060107132A1
• Time in Patent Office: 1,250 Days
• Field of Search: 714/718, 714/738
• US Class Current: 714/718
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a memory failure in a sequence of records corresponding the operating conditions over a period of time that includes the occurrence of the memory failure and further includes executing a software translation module to generate a file of test vectors from the sequence of records that when executed by the ATE reproduce the operating condition over the sampled period of time. The memory under test is tested according to the file of test vectors for the ATE.

Claims

1. A method for testing a memory on automated test equipment (ATE) having a test vector memory, the method comprising:

sampling operating conditions for a memory exhibiting a memory failure, the sampling occurring over a period of time that includes the occurrence of the memory failure;

creating a sequence of records representing the sampled operating conditions over the period of time;

executing a software translation module to translate the sequence of records representing the sampled operating conditions into a file of test vectors for execution by the ATE to generate the sampled operating conditions under which the memory failure occurred;

loading the file of test vectors into the test vector memory;

editing the file of test vectors to apply data signals representing data states that are different than the sampled data states; and

executing the file of test vectors on the ATE to test the memory according to the test vectors.

2. The method of claim 1 wherein creating a sequence of records comprises creating a record for each sample of the operating conditions.

3. The method of claim 2 wherein creating a record for each sample of the operating conditions comprises recording a clock cycle identifier for each sample and recording the logic states for a plurality of signals applied to the memory exhibiting a memory failure.

4. The method of claim 1, further comprising editing the file of test vectors to remove illegal memory operations.

5. The method of claim 1, further comprising editing the file of test vectors to remove signal timing violations.

6. The method of claim 1, further comprising editing the file of test vectors to add timing margin to timing specifications for the memory.

7. The method of claim 1 wherein sampling operating conditions for a memory exhibiting the memory failure comprises capturing for a plurality of clock cycles the logic state of a plurality of signals applied to the memory for each of the respective clock cycles.

8. The method of claim 1, further comprising adding test vectors to the file of test vectors for establishing background data stored by the memory under test.

9. The method of claim 1, further comprising adding test vectors to the file of test vectors for setting operating conditions of the memory under test.

10. A method for testing a memory under test on automated test equipment (ATE), the method comprising:

capturing operating conditions for a memory exhibiting a memory failure in a sequence of records representing the operating conditions over a period of time that includes the occurrence of the memory failure;

executing a software translation module to generate a file of test vectors from the sequence of records representing the operating conditions of the memory that when executed by the ATE reproduce the operating condition over the sampled period of time;

editing the file of test vectors; and

testing the memory under test according to the file of test vectors for the ATE.

11. The method of claim 10 wherein capturing operating conditions in a sequence of records comprises:

sampling the operating conditions at a plurality of clock cycles of a clock signal applied to the memory exhibiting the memory failure; and

creating a record for each sample of the operating conditions.

12. The method of claim 11 wherein creating a record for each sample of the operating conditions comprises recording a clock cycle identifier for each sample and recording the logic states for a plurality of signals applied to the memory exhibiting a memory failure.

13. The method of claim 10 wherein editing the file of test vectors comprises editing the file of test vectors to remove illegal memory operations.

14. The method of claim 10 wherein editing the file of test vectors comprises editing the file of test vectors to remove signal timing violations.

15. The method of claim 10 wherein editing the file of test vectors comprises editing the file of test vectors to add timing margin to timing specifications for the memory.

16. The method of claim 10 wherein editing the file of test vectors comprises editing the file of test vectors to apply data signals representing data states that are different than the sampled data states.

17. The method of claim 10, further comprising adding test vectors to the file of test vectors for establishing background data stored by the memory under test.

18. The method of claim 10, further comprising adding test vectors to the file of test vectors for setting operating conditions of the memory under test.

19. A method for developing an algorithmic test program for automated test equipment (ATE), the method comprising:

sampling operating conditions for a first memory exhibiting a memory failure over a period of time that includes the occurrence of the memory failure;

generating a sequence of records from the sampled operating conditions that include information representing the sampled operating conditions of the memory exhibiting the memory failure over the period of time;

executing a software translation module to generate a file of test vectors from the sequence of records that includes information representing the sampled operating conditions that when executed by the ATE reproduce the operating condition over the sampled period of time and thereby reproduce the memory failure in any memory with the same faults as the first memory;

testing a memory under test according to the file of test vectors for the ATE;

editing the file of test vectors to isolate a failing operating condition that causes the memory under test to exhibit the memory failure; and

developing an algorithmic test program based on the edited file of test vectors that recreates the failing operating condition.

20. The method of claim 19 wherein editing the file of test vectors comprises editing the file of test vectors to remove illegal memory operations.

21. The method of claim 19 wherein editing the file of test vectors comprises editing the file of test vectors to remove signal timing violations.

22. The method of claim 19 wherein editing the file of test vectors comprises editing the file of test vectors to add timing margin to timing specifications for the memory.

23. A system for analyzing a memory exhibiting a memory failure, comprising:

a logic analyzer coupled to the memory, the logic analyzer configured to sample the operating conditions for the memory exhibiting the memory failure over a period of time that includes the occurrence of the memory failure and store the samples in a sequence of records representing the operating conditions;

a computer having a software translation module, the computer configured to execute the translation module to generate a file of test vectors from the sequence of records representing the operating conditions that corresponds to the sampled operating conditions; and

automated test equipment (ATE) having a vector memory in which the file of test vectors can be stored and further having a test interface to which a memory under test is coupled for testing, the ATE configured to execute the file of test vectors when stored in the vector memory to reproduce the operating conditions over the sampled period of time for a memory under test coupled to the test interface and, after executing the file of test vectors, for editing the file of test vectors.

24. The system of claim 23 wherein the logic analyzer comprises a logic analyzer configured to sample for a plurality of clock cycles of a clock signal applied to the memory exhibiting a memory failure the data state for a plurality of signals applied to the memory exhibiting a memory failure at each of the sampled clock cycles.

25. The system of claim 23 wherein the ATE comprises an ATE further having an algorithmic memory for storing an algorithmic test program.

26. The system of claim 23 wherein the ATE configured for editing the file of test vectors is further configured for editing the file of test vectors to remove illegal memory operations.

27. The system of claim 23 wherein the ATE configured for editing the file of test vectors is further configured for editing the file of test vectors to remove signal timing violations.

28. The system of claim 23 wherein the ATE configured for editing the file of test vectors is further configured for editing the file of test vectors to add timing margin to timing specifications for the memory.

29. The system of claim 23 wherein the ATE configured for editing the test vectors is further configured for editing the file of test vectors to apply data signals representing data states that are different than the sampled data states.