Providing high availability in a PCI-Express link in the presence of lane faults
First Claim
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1. A method, comprising:
- discovering a failure of one or more wires comprising a PCI Express interconnect;
determining whether a failure override bit has been set to override the standard PCI Express Polling.Compliance state for the failure on the PCI Express interconnect; and
if the failure override bit has been set, entering PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.
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Abstract
A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling.Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.
23 Citations
19 Claims
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1. A method, comprising:
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discovering a failure of one or more wires comprising a PCI Express interconnect; determining whether a failure override bit has been set to override the standard PCI Express Polling.Compliance state for the failure on the PCI Express interconnect; and if the failure override bit has been set, entering PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A device, comprising:
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a hardware configuration register; a failure discovery unit operable to detect failures of one or more wires comprising a PCI Express interconnect; and a link training and status state machine operable to; determine whether a failure override bit in the hardware configuration register has been set to override a failure on the PCI Express interconnect; and if the failure override bit has been set, enter PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A system, comprising:
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a multi-lane PCI Express interconnect; a first device coupled to the interconnect; a second device, coupled to the interconnect, comprising; a hardware configuration register; a failure discovery unit operable to detect failures of one or more wires comprising a PCI Express interconnect; and a link training and status state machine operable to; determine whether a failure override bit in the hardware configuration register has been set to override a failure on the PCI Express interconnect; and if the failure override bit has been set, allow the second device to enter PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state. - View Dependent Claims (17, 18, 19)
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Specification