Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit

• US 7,353,481 B2
• Filed: 12/30/2005
• Issued: 04/01/2008
• Est. Priority Date: 01/04/2005
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kinoshita, Koichi, Urakawa, Yukihiro
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US11/320,643
• Publication Number:
  US 20060166434A1
• Time in Patent Office: 823 Days
• Field of Search: 716/10, 716/13, 716/14, 326/101, 323/364, 438/618, 438/622
• US Class Current: 716/113
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.

Claims

1. A computer implemented method for designing a semiconductor integrated circuit comprising:

placing a first power line on a first interconnection layer;

placing a dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and

electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.

2. The computer implemented method of claim 1, wherein the dummy pattern and the first power line are connected by a plurality of dummy vias having a long axis in the direction of the first power line.

3. The computer implemented method of claim 1, further comprising:

placing a second power line on a third interconnection layer positioned just above the dummy pattern, the second power line extending in a same direction as the first power line; and

electrically connecting the dummy pattern to the second power line.

4. The computer implemented method of claim 1, further comprising:

placing a plurality of signal lines on the second interconnection layer, each of the signal lines having a line width smaller than the first power line,

wherein a number of the signal lines positioned just above the first power line is limited by placement limitation data.

5. The computer implemented method of claim 4, further comprising:

verifying a timing of a circuit based on placement result of the first power line, the dummy pattern and the signal lines; and

diverting the signal lines from an upper layer of the first power line based on a result of timing verification.

6. The computer implemented method of claim 5, further comprising:

optimizing a position of the dummy pattern to be placed just above the first power line based on the result of the timing verification;

optimizing a size of the dummy pattern to enlarge a crossover area between the dummy pattern and the first power line on a plane based on the result of the timing verification; and

storing optimized data of the dummy pattern in an optimization storage.

7. The computer implemented method of claim 6, further comprising:

verifying optimized data of the dummy pattern and storing a verification result of the optimized data in a verification storage; and

deleting the optimized data of the dummy pattern in the optimization storage based on the verification result of the optimized data.

8. The computer implemented method of claim 1, wherein the dummy pattern is placed just above the first power line with priority to a plurality of signal lines provided on the second interconnection layer, based on placement limitation data.

9. A semiconductor integrated circuit comprising:

a semiconductor substrate;

a first power line provided on the semiconductor substrate;

a first insulator dielectric having a relative dielectric constant equal to or lower than silicon oxide provided on the first power line;

a dummy line embedded in the first insulator dielectric and extending parallel to a direction of the first power line; and

a plurality of first dummy vias embedded in the first insulator dielectric and connected to the first power line and the dummy line.

10. The semiconductor integrated circuit of claim 9, wherein each of the first dummy vias has a long axis parallel to the direction of the first power line.

11. The semiconductor integrated circuit of claim 9, further comprising a diffusion barrier film having a higher relative dielectric constant than the dielectric constant of the first insulator dielectric, and provided on the first insulator dielectric.

12. The semiconductor integrated circuit of claim 9, wherein the first insulator dielectric is composed of a plurality of films having different relative dielectric constants respectively.

13. The semiconductor integrated circuit of claim 9, further comprising:

a second insulator dielectric having a relative dielectric constant equal to or less than silicon oxide provided on the dummy line;

a second power line embedded in the second insulator dielectric and extending in a same direction as the direction of the first power line;

a plurality of second dummy vias embedded in the second insulator dielectric and connected to the second power line and the dummy line.

14. A semiconductor integrated circuit having multi-level interconnects, comprising:

a plurality of first power lines provided on a semiconductor substrate;

a first insulator dielectric having a relative dielectric constant equal to or lower than silicon oxide provided on the first power lines; and

a plurality of dummy lines embedded in the first insulator dielectric above one of the first power lines, in an area corresponding to a planar area where a density of signal lines in the multi-level interconnects is low, each of the dummy lines having a long axis parallel to a direction of the first power lines.

15. The semiconductor integrated circuit of claim 14, further comprising a plurality of first dummy vias connected to the first power lines and the dummy lines,

wherein each of the first dummy vias has a long axis parallel to the direction of the first power lines.

16. The semiconductor integrated circuit of claim 15, further comprising:

a second insulator dielectric having a relative dielectric constant equal to or lower than silicon oxide provided on the dummy lines;

a plurality of second power lines embedded in the second insulator dielectric, positioned just above the dummy lines and extending in a same direction as the direction of the first power lines; and

a plurality of second dummy vias embedded in the second insulator dielectric and connected to one of the second power lines and the dummy lines.

17. The semiconductor integrated circuit of claim 14, further comprising a plurality of diffusion barrier films provided on the first insulator dielectric and the first power lines.