Flow definition language for designing integrated circuit implementation flows
First Claim
1. A method for generating a hierarchical flow definition language for designing integrated circuit implementation flows, the method comprising:
- generating a plurality of command file templates defining tasks associated with a physical chip design, each of which are customized through one or more parameters;
generating a plurality of stage definition files defining relational constraints of execution order of tasks in associated stages of said physical chip design, execution order between stages of said physical chip design, and values for parameters used within a corresponding stage, wherein each of said plurality of stage definition files is comprised of at least one of said plurality of command file templates; and
generating a plurality of subflow definition files defining relational constraints between stages and subflows in said physical chip design, wherein each said plurality of subflow definition files is comprised of at least one of said plurality of stage definition files.
6 Assignments
0 Petitions
Accused Products
Abstract
An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order of a plurality of tasks in the hierarchical collection of stages. Parameters customize the plurality of tasks. The relational constraints and parameters are hierarchically defined, such that higher order definitions in the hierarchical collection of stages override lower level definitions of the relational constraints and parameterized knobs.
-
Citations
24 Claims
-
1. A method for generating a hierarchical flow definition language for designing integrated circuit implementation flows, the method comprising:
-
generating a plurality of command file templates defining tasks associated with a physical chip design, each of which are customized through one or more parameters; generating a plurality of stage definition files defining relational constraints of execution order of tasks in associated stages of said physical chip design, execution order between stages of said physical chip design, and values for parameters used within a corresponding stage, wherein each of said plurality of stage definition files is comprised of at least one of said plurality of command file templates; and generating a plurality of subflow definition files defining relational constraints between stages and subflows in said physical chip design, wherein each said plurality of subflow definition files is comprised of at least one of said plurality of stage definition files. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A hierarchical flow definition language data structure embodied in a computer-readable medium, the hierarchical flow definition language data structure being arranged to allow an application executed by a processor of a computer system to generate integrated circuit implementation flows, the computer-readable medium comprising:
-
a plurality of command file templates defining tasks associated with a physical chip design, each of which are customized through one or more parameters; a plurality of stage definition files defining relational constraints of execution order of tasks in associated stages of said physical chip design, execution order between stages of said physical chip design, and values for parameters used within a corresponding stage, wherein each of said plurality of stage definition files is comprised of at least one of said plurality of command file templates; and a plurality of subflow definition files defining relational constraints between stages and subflows in said physical chip design, wherein each said plurality of subflow definition files is comprised of at least one of said plurality of stage definition files. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
-
17. A data processing system comprising:
-
a processor; and a memory coupled to the processor, the memory configured to store a set of data structures arranged to allow an application executed by the processor to generate integrated circuit implementation flows, the memory comprising; a plurality of command file templates defining tasks associated with a physical chip design, each of which are customized through one or more parameters; a plurality of stage definition files defining relational constraints of execution order of tasks in associated stages of said physical chip design, execution order between stages of said physical chip design, and values for parameters used within a corresponding stage, wherein each of said plurality of stage definition files is comprised of at least one of said plurality of command file templates; and a plurality of subflow definition files defining relational constraints between stages and subflows in said physical chip design, wherein each said plurality of subflow definition files is comprised of at least one of said plurality of stage definition files. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
-
Specification