CMOS image sensor and method for fabricating the same

• US 7,354,789 B2
• Filed: 11/04/2004
• Issued: 04/08/2008
• Est. Priority Date: 11/04/2003
• Status: Expired due to Fees

• Current Assignee: Columba Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Han, Chang Hun
• Primary Examiner(s): Toledo; Fernando L.
• Assistant Examiner(s): Jefferson; Quovaunda
• Application Number:
  US10/982,643
• Publication Number:
  US 20050093036A1
• Time in Patent Office: 1,251 Days
• Field of Search: 438/48, 438/290, 438/449, 438/450, 438/451, 438/328, 438197-199, 438/510, 438/514, 438/527, 438/530, 438/532, 438/73, 438/78, 438/292, 438/461, 438/FOR.187, 438/FOR.216, 438/57, 438/149, 438/151, 257290-292, 257/E25.032, 257/E27.133, 257/E21.632, 257/E21.63
• US Class Current: 438/57
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

CMOS image sensor and method for fabricating the same, the CMOS image sensor including a second conductive type semiconductor substrate having an active region and a device isolation region defined therein, wherein the active region has a photodiode region and a transistor region defined therein, a device isolating film in the semiconductor substrate of the device isolation region, a first conductive type impurity region in the semiconductor substrate of the photodiode region, the first conductive type impurity region being spaced a distance from the device isolation film, and a second conductive type first impurity region in the semiconductor substrate between the first conductive type impurity region and the device isolation film, thereby reducing generation of a darkcurrent at an interface between the photodiode region and a field region.

Claims

1. A method for fabricating a CMOS image sensor, comprising the steps of:

forming a device isolation film in a second conductive type semiconductor substrate, defining an active region having a photodiode region and a transistor region;

forming a gate insulating film and a gate electrode on the transistor region of the semiconductor substrate;

forming a lightly doped first conductive type impurity region in the photodiode region of the semiconductor substrate;

forming a medium concentration second conductive type impurity region at a surface of the lightly doped first conductive type impurity region; and

forming a heavily doped second conductive type impurity region adjacent to the device isolation film in the photodiode region of the substrate, the heavily doped second conductive type impurity region having a depth the same as a depth of the device isolation film, or a depth of the lightly doped first conductive type impurity region.

2. The method as claimed in claim 1, wherein the heavily doped second conductive type impurity region has a predetermined width.

3. A method for fabricating a CMOS image sensor, comprising the steps of:

forming a device isolation film in a second conductive type semiconductor substrate, defining an active region having a photodiode region and a transistor region;

forming a gate insulating film and a gate electrode on the transistor region of the semiconductor substrate;

forming a lightly doped first conductive type impurity region in the photodiode region of the semiconductor substrate;

forming a medium concentration second conductive type impurity region at a surface of the lightly doped first conductive type impurity region; and

forming a heavily doped second conductive type impurity region adjacent to the device isolation film in the photodiode region of the substrate, the heavily doped second conductive type impurity region having a width the same as a depth of the medium concentration second conductive type impurity region.

4. The method as claimed in claim 3, wherein the heavily doped second conductive type impurity region has a dept the same as a depth of the device isolation film, or a depth of the lightly doped first conductive type impurity region.

5. The method as claimed in claim 3, further comprising forming an insulating layer on an entire surface of the substrate inclusive of the gate electrode.

6. The method as claimed in claim 5, wherein forming the insulating layer is performed after forming the lightly doped first conductive type impurity region and before forming the medium concentration second conductive type impurity region.

7. The method as claimed in claim 5, further comprising anisotropically etching the insulating layer to form spacers at sidewalls of the gate electrode.

8. The method as claimed in claim 7, wherein the steps of forming the insulating layer and anisotropically etching the insulating layer are performed after forming the lightly doped first conductive type impurity region and before forming the medium concentration second conductive type impurity region.

9. The method as claimed in claim 3, wherein the semiconductor substrate comprises an epitaxial layer on a heavily doped second conductive type substrate.

10. The method as claimed in claim 3, further comprising forming a photoresist film pattern on the substrate so as to expose the photodiode region adjacent to the device isolation film.

11. The method as claimed in claim 10, wherein the exposed photodiode region has a predetermined width.

12. A method for fabricating a CMOS image sensor, comprising the steps of:

forming a device isolation film in a second conductive type semiconductor substrate, defining an active region having a photodiode region and a transistor region;

forming a gate insulating film and a gate electrode on the transistor region of the semiconductor substrate;

forming a lightly doped first conductive type impurity region in the photodiode region of the semiconductor substrate;

forming an insulating layer on an entire surface of the substrate inclusive of the gate electrode;

selectively removing the insulating layer to expose the device isolating film and a predetermined portion of the photodiode region adjacent to the device isolating film,

forming a photoresist film pattern to expose the photodiode region and the insulating layer; and

injecting second conductive type impurity ions at a medium concentration into the photodiode region using the insulating layer and the photoresist pattern as a mask, to form medium concentration second conductive type impurity regions at an interface of the device isolating film and the photodiode region and at a surface of the lightly doped first conductive type impurity region, the medium concentration second conductive type impurity region at the interface of the device isolating film and the photodiode region having a depth deeper than a depth of the medium concentration second conductive type impurity region at the surface of the hightly doped first conductive type impurity region.

13. The method as claimed in claim 12, wherein the medium concentration second conductive type impurity region at the interface of the device isolating film and the photodiode region has a depth the same with a depth of the device isolation film.

14. The method as claimed in claim 12, wherein the medium concentration second conductive type impurity region at the interface of the device isolating film and the photodiode region has a width the same with a depth of the medium concentration second conductive type impurity region at the surface of the lightly doped first conductive type impurity region.

15. The method as claimed in claim 12, wherein the insulating film exposes the photodiode region by a width in a range of 400˜

600 Å

.

16. The method as claimed in claim 12, wherein the insulating layer comprises one of an insulating film formed from SiH₄, a USG (Undoped Silicate Glass) film, a BPSG (Boro Phosphorous Silicate Glass) film, or a TEOS (tetra Ethyl Ortho Silicate) film.

17. The method of claim 16, wherein the insulating film comprises said USG film, and forming the insulating layer comprises depositing said USG film by high density plasma chemical vapor deposition.

18. The method as claimed in claim 12, wherein the insulating film has a thickness smaller than a depth of the device isolation film by 300˜

500Å

.

19. The method as claimed in claim 12, wherein the insulating film has a thickness of 2000˜

3000 Å

.

20. The method as claimed in claim 12, wherein the semiconductor substrate comprises an epitaxial layer on a heavily doped second conductive type substrate.