Method for fabricating semiconductor devices using strained silicon bearing material

• US 7,354,815 B2
• Filed: 11/17/2004
• Issued: 04/08/2008
• Est. Priority Date: 11/18/2003
• Status: Expired due to Fees

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US10/992,596
• Publication Number:
  US 20050118754A1
• Time in Patent Office: 1,238 Days
• Field of Search: 438/199, 438/458, 438/312
• US Class Current: 438/199
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing. Preferably, the second spacing placing the film of material in either a tensile or compressive mode across the entirety of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method includes processing the film of material to form a first region and a second region within the film of material. The first region and the second region are characterized by either the tensile or compressive mode. Preferably, both the first and second regions in their entirety are characterized by either the tensile or compressive mode. The method includes processing the first region of the film of material while maintaining the second region characterized by either the tensile or the compressive mode to form an opposite characteristic from the second region. The opposite characteristic is a tensile mode if the second region is in the compressive mode and the opposite characteristic is the compressive mode if the second region is in the tensile mode.

Claims

1. A method of manufacturing an integrated circuit on semiconductor substrates, the method comprising:

providing a semiconductor substrate chatacterized by a first lattice with a first structure and a first spacing, the semiconductor substrate having an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in either a tensile or compressive mode across the entirety of the film of material relative to the semiconductor substrate with the first structure and the first spacing;

processing the film of material to form a first region and a second region within the film of material, the first region and the second region being characterized by either the tensile or compressive mode; and

processing the first region of the film of material while maintaining the second region characterized by either the tensile or the compressive mode to form an opposite characteristic from the second region, the opposite characteristic being a tensile mode if the second region is in the compressive mode and the opposite characteristic being the compressive mode if the second region is in the tensile mode.

2. The method of claim 1 wherein the second spacing places the film of material in the tensile mode.

3. The method of claim 1 wherein the second spacing places the film of material in the compressive mode.

4. The method of claim 1 wherein the processing of the first region comprises:

forming a source recessed region and a drain recessed region with a channel region between the source recessed region and the drain recessed region;

depositing an epitaxial silicon material with a third structure and a third lattice constant, the third lattice constant being different from the second lattice constant;

doping the epitaxial silicon material to cause the opposite characteristic within the channel region, the opposite characteristic being either the compressive mode or the tensile mode.

5. The method of claim 4 wherein the dopant is selected from germanium or carbon.

6. The method of claim 4 wherein the first region comprises N-type MOS type transistors.

7. The method of claim 1 wherein the first region comprises a plurality of N MOS transistors and the second region comprises a plurality of P MOS transistors.

8. The method of claim 1 wherein the film of material is strained silicon bearing material.

9. The method of claim 8 wherein the strained silicon bearing material is overlying an epitaxial silicon-germanium material, the epitaxial silicon-germanium material overlying the semiconductor substrate.

10. The method of claim 1 wherein the processing of the first region comprises:

forming a capping layer overlying a channel region to cause stress therein, the channel region being coupled between a source region and a drain region of an MOS transistor.

11. The method of claim 10 wherein the capping layer is provided by depositing a thickness of silicon nitride bearing material overlying the channel region.

12. The method of claim 1 wherein the first lattice structure is for a lattice structure for a silicon substrate and the second lattice structure is for a strained silicon material.

13. The method of claim 12 further comprising forming an insulating material overlying the semiconductor substrate, the insulating material being between the semiconductor substrate and the film of material.

14. The method of claim 12 wherein the film of material consisting of strained silicon bearing material is overlying an epitaxial silicon-germanium material.