Trench-gate transistor with ono gate dielectric and fabrication process therefor

• US 7,354,829 B2
• Filed: 10/28/2004
• Issued: 04/08/2008
• Est. Priority Date: 01/14/2000
• Status: Expired due to Fees

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Aoki, Takaaki, Soga, Hajime, Kuroyanagi, Akira, Suzuki, Mikimasa, Tomatsu, Yutaka
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US10/974,838
• Publication Number:
  US 20050090060A1
• Time in Patent Office: 1,258 Days
• Field of Search: 438/268, 438270-272, 438/287, 438/589, 257/E21.655, 257/E29.201, 257/E21.419
• US Class Current: 438/272
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.

Claims

1. A method for manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate having a trench formed thereon, the trench including an opening portion, inner wall portions and a bottom portion;

forming a first oxide film on the opening portion, the inner wall portions, and the bottom portion of the trench;

forming a nitride film on the first oxide film;

partially removing the nitride film so that the first oxide film is exposed at a first region at the opening portion of the trench and at a second region on the bottom portion of the trench;

simultaneously forming a second oxide film on the nitride film on the inner wall portions, and on the exposed first oxide film at the first region and the second region and thickening the second oxide film at the first region and the second region by thermal oxidation.

2. The method according to claim 1, wherein the second oxide film is formed so that a total thickness of the first oxide film and the second oxide film disposed on one of the first region and the second region is thicker than a total thickness of the first oxide film, the nitride film, and the second oxide film disposed on one of the inner wall portions.

3. A method for manufacturing a trench-gate type transistor, comprising:

forming a semiconductor substrate having a trench thereon, the trench including an opening portion, inner wall portions and a bottom portion; and

forming a gate insulating film on the trench, wherein the formation of the gate insulating film includes;

forming a first oxide film on the opening portions, the inner wall portions and the bottom portion of the trench;

locally disposing an oxidation preventive film on the first oxide film;

etching the oxidation preventive film to expose portions of the first oxide film at the opening portion and the bottom portion of the trench; and

simultaneously forming a second oxide film on the exposed portions of the first oxide film and the oxidation preventive film, with the oxidation preventive film locally interposed therebetween and thickening the second oxide film in the exposed portions by thermal oxidation.

4. The method according to claim 3, wherein the oxidation preventive film is a nitride film.

5. A method for manufacturing a trench-gate type transistor, comprising:

preparing a semiconductor substrate composed of a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer, and a first conductivity type third semiconductor layer;

forming a trench on the semiconductor substrate from a main surface of the semiconductor substrate at a side of the first semiconductor layer, the trench penetrating the first semiconductor layer and the second semiconductor layer to reach the third semiconductor layer, the trench including an opening portion, inner wall portions and a bottom portion;

forming a gate insulating film on the trench by forming a first oxide film on the opening portion, the inner wall portions and the bottom portion of the trench;

forming a nitride film on the first oxide film;

removing a part of the nitride film to expose a part of the first oxide film at the opening portion and the bottom portion; and

simultaneously forming a second oxide film on the nitride film and on the exposed part of the first oxide film at the opening portion and the bottom portion and thickening the second oxide film at the opening portion and the bottom portion by thermal oxidation; and

forming a gate electrode in the trench.

6. The method according to claim 5, wherein:

when the gate insulating film is formed, the nitride film is partially removed to expose an end portion thereof at a side of the main surface of the semiconductor substrate, a location of the end portion defining a distance from the main surface that is smaller than that of a boundary between the first semiconductor layer and the second semiconductor layer.

7. The method according to claim 5, wherein:

the second oxide film is simultaneously formed on the nitride film and on the exposed part of the first oxide film at the opening portion and the bottom portion so that a total thickness of the gate insulating film at the exposed part of the first oxide film at one of the opening portion and the bottom portion is thicker than that on the nitride film at one of the inner wall portions.