Technique for forming a contact insulation layer with enhanced stress transfer efficiency

• US 7,354,838 B2
• Filed: 11/29/2005
• Issued: 04/08/2008
• Est. Priority Date: 04/29/2005
• Status: Active Grant

• Current Assignee: Innovative Foundry Technologies LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kammler, Thorsten, Wei, Andy, Lenski, Markus
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Parker, John M.
• Application Number:
  US11/288,673
• Publication Number:
  US 20060246641A1
• Time in Patent Office: 861 Days
• Field of Search: 438/231, 438/232, 438/304, 438/558, 438562-564, 438/197, 438/299, 438/301, 438/510, 438303-307, 438/545, 438/554, 438/559
• US Class Current: 438/303
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

Claims

1. A method, comprising:

forming a transistor element comprising a gate electrode structure including at least an inner spacer element and an outer spacer element, wherein forming said transistor element comprises;

forming a gate electrode above a semiconductor region;

forming said at least one inner spacer element adjacent the sidewalls of said gate electrode;

forming an etch stop layer to separate said at least one inner spacer element and said outer spacer element; and

forming drain/source regions using said inner and outer spacer elements as the implantation mask; and

wherein forming said outer spacer element comprises depositing said etch stop layer, depositing a spacer material layer, anisotropically etching said spacer material layer to form said outer spacer element and etching said etch stop layer using said outer spacer element as an etch mask;

removing said outer spacer element;

forming a contact liner layer above said transistor element; and

forming a silicide region on said gate electrode and said drain/source region prior to forming said contact liner layer, wherein said outer spacer element is removed prior to forming said silicide region.

2. The method of claim 1, wherein forming said contact liner layer comprises depositing a dielectric material, using deposition parameters to achieve a predefined internal stress in said contact liner layer.

3. The method of claim 1, further comprising performing a cleaning process prior to forming said silicide region.

4. The method of claim 3, wherein said cleaning process is performed on the basis of an etch chemistry configured to selectively etch said outer spacer element with respect to said etch stop layer.

5. The method of claim 4, wherein said cleaning process is controlled so as to substantially completely remove said outer spacer element.

6. The method of claim 1, further comprising forming an offset spacer element adjacent said sidewalls of said gate electrode prior to forming said inner and outer spacer elements.

7. The method of claim 6, further comprising forming a liner prior to forming said inner spacer element, said liner being configured to act as an etch stop layer during the formation of said inner spacer element.

8. The method of claim 1, wherein said inner spacer element is comprised of one of silicon dioxide and silicon nitride.

9. The method of claim 1, wherein said outer spacer element is comprised of one of silicon nitride and silicon dioxide and said etch stop layer is comprised of the other one of said silicon nitride and silicon dioxide.

10. A method, comprising:

forming a first transistor element having a first gate electrode structure including at least an inner and an outer spacer element;

forming a second transistor element having a second gate electrode structure including at least an inner and an outer spacer element, wherein forming said outer spacer elements comprises depositing an etch stop layer, depositing a spacer material layer, anisotropically etching said spacer material layer to form said outer spacer elements and etching said etch stop layer using said outer spacer element as an etch mask;

removing said outer spacer elements of said first and second gate electrode structures;

forming a first contact liner layer having a first internal stress above said first transistor element and a second contact liner layer having a second internal stress above said second transistor element; and

forming a silicide region on said first and second gate electrodes and drain/source regions of said first and second transistor elements prior to forming said contact liner layer, wherein said outer spacer elements are removed prior to forming said silicide regions.

11. The method of claim 10, wherein said first and second internal stresses are different.

12. The method of claim 10, wherein forming said first and second contact liner layers comprises depositing a contact liner layer having said first internal stress above said first and second transistor elements and selectively relaxing said contact liner layer formed above said second transistor element to obtain said second internal stress.

13. The method of claim 10, wherein forming said first and second contact liner layers comprises depositing a contact liner layer having said first internal stress above said first and second transistor elements, selectively removing a portion of the contact liner layer above said second transistor element and depositing a further contact liner layer having said second internal stress above said first and second transistor elements.

14. The method of claim 10, wherein forming said first and second transistor elements comprises:

forming a first and second gate electrode above a semiconductor region;

forming said at least one inner spacer element adjacent the sidewalls of said first and second gate electrodes;

forming an etch stop layer to separate said at least one inner spacer element and said outer spacer element; and

forming drain/source regions using said inner and outer spacer elements as the implantation mask.

15. The method of claim 10, wherein forming said contact liner layer comprises depositing a dielectric material, using deposition parameters to achieve a predefined internal stress in said contact liner layer.

16. The method of claim 10, further comprising performing a cleaning process prior to forming said silicide regions.

17. The method of claim 16, wherein said cleaning process is performed on the basis of an etch chemistry configured to selectively etch said outer spacer elements with respect to said etch stop layer.

18. The method of claim 17, wherein said cleaning process is controlled so as to substantially completely remove said outer spacer elements.

19. The method of claim 15, further comprising forming an offset spacer element prior to forming said inner and outer spacer elements.