Method of trimming technology
First Claim
1. A method of trimming a feature in a pattern formed in a photoresist layer on a substrate, comprising:
- providing a substrate;
forming a bilayer stack comprised of a top photoresist layer and an organic underlayer on said substrate, said organic underlayer is thicker than said top photoresist layer;
forming a pattern having a feature with a first width in said top photoresist layer;
transferring said pattern through the organic underlayer with a first plasma etch step to produce a pattern that has a feature with a first width and sidewalls; and
trimming said pattern with a second plasma etch step to give a pattern in the bilayer stack having a feature with a second width and sidewalls, said second width is smaller than said first width.
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Accused Products
Abstract
A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.
397 Citations
37 Claims
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1. A method of trimming a feature in a pattern formed in a photoresist layer on a substrate, comprising:
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providing a substrate; forming a bilayer stack comprised of a top photoresist layer and an organic underlayer on said substrate, said organic underlayer is thicker than said top photoresist layer; forming a pattern having a feature with a first width in said top photoresist layer; transferring said pattern through the organic underlayer with a first plasma etch step to produce a pattern that has a feature with a first width and sidewalls; and trimming said pattern with a second plasma etch step to give a pattern in the bilayer stack having a feature with a second width and sidewalls, said second width is smaller than said first width. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of forming a gate electrode in a MOSFET, comprising:
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providing a substrate with isolation regions formed therein and with a gate stack comprised of a gate layer on a gate dielectric layer formed on said substrate between said isolation regions; forming a bilayer stack comprised of a top photoresist layer and an organic underlayer on said gate layer, said organic underlayer is thicker than said top photoresist layer; forming a pattern having a feature with a first width in said top photoresist layer; transferring said pattern through the organic underlayer with a first plasma etch step to produce a pattern that has a feature with a first width and sidewalls; trimming said pattern in said top photoresist and organic underlayer with a second plasma etch step to give a pattern in the bilayer stack having a feature with a second width and sidewalls, said second width is smaller than said first width; and transferring said trimmed pattern with said second width through said gate layer with a third plasma etch step to form a gate electrode. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of forming a gate electrode in a MOSFET, comprising:
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providing a substrate with isolation regions formed therein and with a gate stack comprised of a gate layer on a gate dielectric layer formed on said substrate between said isolation regions; forming a bilayer stack comprised of a top photoresist layer with a surface region and an organic underlayer on said gate layer, said organic underlayer is thicker than said top photoresist layer; patternwise exposing a surface region of the top photoresist layer; selectively silylating portions of the top photoresist layer to give silylated portions having a first width; forming a pattern having a feature with a first width in said top photoresist layer by a first plasma etch step that removes non-silylated portions in the surface region and the underlying top photoresist layer; transferring said pattern through the organic underlayer with a second plasma etch step, said pattern has a feature with sidewalls and a first width; trimming said pattern in said top photoresist layer and organic underlayer with a third plasma etch step to give a pattern in the bilayer stack having a feature with sidewalls and a second width, said second width is smaller than said first width; transferring said trimmed pattern with said second width through said gatelayer with a fourth plasma etch step to form a gate electrode having a second width. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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Specification