Semiconductor device and method for high-k gate dielectrics

• US 7,355,235 B2
• Filed: 12/22/2004
• Issued: 04/08/2008
• Est. Priority Date: 12/22/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chih-Hao, Chen, Shang-Chih, Tsai, Ching-Wei
• Primary Examiner(s): BRYANT, KIESHA ROSE
• Application Number:
  US11/020,377
• Publication Number:
  US 20060131675A1
• Time in Patent Office: 1,203 Days
• Field of Search: 257/310
• US Class Current: 257/310
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.

Claims

1. A semiconductor device, comprising:

a substrate;

a nitrogen-containing, substantially metal-free layer over the substrate;

a high-k dielectric material having nitrogen over the nitrogen-containing layer;

wherein the nitrogen percentage in the high-k dielectric material is lower than that in the nitrogen-containing layer; and

a gate electrode material over the high-k dielectric material.

2. The semiconductor device of claim 1, wherein the nitrogen-containing layer is low-trap nitride.

3. The semiconductor device of claim 2, wherein the low-trap nitride is jet vapor deposited (JVD) silicon nitride.

4. The semiconductor device of claim 2, wherein the low-trap nitride has an interface state density less than about 5*10¹¹ c/cm².

5. The semiconductor device of claim 1, wherein the nitrogen-containing layer is less than about 3 nm thick.

6. The semiconductor device of claim 1, wherein the high-k gate dielectric further comprises a material selected from the group consisting essentially of HFSiON, amorphous HfSiON, Ta₂O₅, TiO₂, Al₂O₃, ZrO₂, HfO₂, Y₂O₃, La₂O₃, aluminates, silicates, HfO₂, HfSiO_x, HfAlO_x, Al₂O₃, TiO₂, PbTiO₃, BaTiO₃, SrTiO₃, and PbZrO₃, and combinations thereof.

7. The semiconductor device of claim 1, wherein the substrate comprises Si, strained Si, Ge, strained Ge, SiC, strained SiGe, SOI, GOI, GaAs, a stacked arrangement of layers, or a combination thereof.

8. The semiconductor device of claim 1, wherein the gate electrode material is selected from the group consisting essentially of silicon, germanium, metal silicide, metal, and combinations thereof.

9. The semiconductor device of claim 1, further comprising a second nitrogen-containing layer over the high-k dielectric layer.

10. The semiconductor device of claim 9, wherein the second nitrogen-containing layer comprises JVD silicon nitride.

11. A semiconductor device, comprising:

a substrate;

a nitrogen-containing layer over the substrate, wherein the nitrogen-containing layer is substantially void of metal and is deposited using jet vapor deposition (JVD);

a high-k dielectric material having nitrogen over the nitrogen-containing layer wherein the high-k dielectric layer has a lower percentage of nitrogen than does the nitrogen-containing layer; and

a gate electrode material over the high-k dielectric material.

12. The semiconductor device of claim 11, wherein the nitrogen-containing layer is low-trap nitride.

13. The semiconductor device of claim 12, wherein the low-trap nitride has an interface state density less than about 5*10¹¹ c/cm².

14. The semiconductor device of claim 11, wherein the nitrogen-containing layer is less than about 3 nm thick.

15. The semiconductor device of claim 11, wherein the substrate comprises Si, strained Si, Ge, strained Ge, SiC, strained SiGe, SOI, GOI, GaAs, a stacked arrangement of layers, or a combination thereof.

16. The semiconductor device of claim 11, further comprising a second nitrogen-containing layer over the high-k dielectric layer.

17. The semiconductor device of claim 16, wherein the second nitrogen-containing layer comprises JVD silicon nitride.

18. A semiconductor device, comprising:

a substrate;

a non-metal, nitrogen-containing interfacial layer over the substrate;

a high-k dielectric material having nitrogen over the interfacial layer wherein the nitrogen content in the high-k dielectric material is lower than the nitrogen content in the interfacial layer;

a nitrogen-containing layer on the high-k dielectric material; and

a gate electrode material over the nitrogen-containing layer.

19. The semiconductor device of claim 18, wherein the nitrogen-containing layer is low-trap nitride.

20. The semiconductor device of claim 19, wherein the low-trap nitride is deposited using jet vapor deposition (JVD).

21. The semiconductor device of claim 19, wherein the low-trap nitride has an interface state density less than about 5*10¹¹ c/cm².

22. The semiconductor device of claim 18, wherein the reaction layer is less than about 0.5 nm.

23. The semiconductor device of claim 18, wherein the high-k dielectric material is less than about 5 nm thick.

24. The semiconductor device of claim 18, wherein the high-k dielectric material further comprises any material from the group consisting essentially of HfSiON, amorphous HfSiON, Ta₂O₅, TiO₂, Al₂O₃, ZrO₂, HfO₂, Y₂O₃, La₂O₃, aluminates, silicates, HfO₂, HfSiO_x, HfAlO_x, Al₂O₃, TiO₂, PbTiO₃, BaTiO₃, SrTiO₃, and PbZrO₃, or combinations thereof.

25. The semiconductor device of claim 18, wherein the substrate comprises Si, strained Si, Ge, strained Ge, SiC, strained SiGe, SOI, GOI, GaAs, a stacked arrangement of layers, or a combination thereof.

26. The semiconductor device of claim 18, wherein the interfacial layer consists essentially of approximately stoichiometric silicon nitrite, non-stoichiometric silicon nitride, and combinations thereof.