Shield plate for limiting cross coupling between floating gates

• US 7,355,237 B2
• Filed: 02/13/2004
• Issued: 04/08/2008
• Est. Priority Date: 02/13/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Lutze, Jeffrey W.
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US10/778,634
• Publication Number:
  US 20050180186A1
• Time in Patent Office: 1,516 Days
• Field of Search: 257/314, 257315-317, 257/320, 257/390, 257/329, 257/319, 257/318
• US Class Current: 257/314
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.

Claims

1. A non-volatile memory system, comprising:

a set of floating gate stacks, the set comprising a plurality of successive adjacent pairs of floating gate stacks connected in series, each floating gate stack comprising a control gate above a floating gate; and

a set of shields comprising a shield for each adjacent pair of floating gate stacks, each respective shield comprises an epitaxial portion and is positioned between two respective adjacent floating gate stacks of an adjacent pair of floating gate stacks, each respective shield extends to a height which is part way between top and bottom portions of floating gates of the two respective adjacent floating gate stacks.

2. A non-volatile memory system according to claim 1, wherein:

said set of floating gate stacks is provided on a substrate having active and inactive regions, said shields are positioned at said active regions but not at said inactive regions.

3. A non-volatile memory system according to claim 1, wherein:

each respective shield extends to a height which is suitable for reducing coupling between two respective adjacent floating gates of an adjacent pair of floating gate stacks.

4. A non-volatile memory system according to claim 1, wherein:

said adjacent pairs of floating gate stacks are connected in series in a common NAND string, and each respective shield is positioned between two adjacent floating gate stacks along said common NAND string.

5. A non-volatile memory system according to claim 1, wherein:

said shields comprise epitaxially grown silicon.

6. A non-volatile memory system according to claim 1, wherein:

said shields are electrically connected to source/drain regions associated with said floating gate stacks and do not have any electrical connection other than to said source/drain regions.

7. A non-volatile memory system according to claim 1, wherein:

said epitaxial portions comprise a dopant.

8. A non-volatile memory system according to claim 1, wherein:

said floating gate stacks are provided in an array of flash memory devices.

9. A non-volatile memory system according to claim 1, wherein:

said floating gate stacks are provided in an array of multi-state flash memory devices.

10. A non-volatile memory system according to claim 1, wherein:

said floating gate stacks are provided in an array of NAND flash memory devices.

11. A non-volatile memory system according to claim 1, further comprising:

insulating material fully covering a top side of each shield, the top side of each shield faces away from a substrate on which each shield is grown.

12. A non-volatile memory system according to claim 1, further comprising:

insulating material covering each shield fully on opposing sides and fully on a top side of each shield, the top side of each shield faces away from a substrate on which each shield is grown.

13. A non-volatile memory system according to claim 1 further comprising:

tapered spacers on opposing sides of each floating gate stack, each tapered spacer extends from a top side of a respective shield to a top of the floating gate stack.

14. A non-volatile memory system according to claim 1, wherein:

spacers are provided on opposing sides of each floating gate stack, each spacer extends between control gates of adjacent floating gate stacks, and from a top side of a respective shield to a top of the adjacent floating gate stacks.

15. A non-volatile memory system, comprising:

a set of non-volatile storage elements, each of said non-volatile storage elements includes a source, a drain, and a floating gate;

shields positioned between at least a subset of said floating gates and electrically connected to sources and drains of said non-volatile storage elements, each shield extends to a height which is between top and bottom portions of the floating gates; and

insulating material covering each shield fully on opposing sides and fully on a top side of each shield.

16. A non-volatile memory system according to claim 15, wherein:

each respective shield is positioned between two respective adjacent floating gates and is electrically connected to a shared source/drain region for said two respective adjacent floating gates.

17. A non-volatile memory system according to claim 15, wherein:

said shields comprise epitaxially grown silicon.

18. A non-volatile memory system according to claim 15, wherein:

said non-volatile storage elements comprise an array of NAND flash memory devices;

said array of NAND flash memory devices includes a set of NAND strings;

each of said NAND strings include a set of said floating gate stacks, each floating gate stack includes one of said floating gates; and

each respective shield is positioned between two respective adjacent floating gate stacks along a common NAND string and is electrically connected to a shared source/drain region for said two respective adjacent floating gate stacks.

19. A non-volatile memory system according to claim 15, wherein:

said non-volatile storage elements are multi-state NAND flash memory devices.

20. A non-volatile memory system according to claim 15, wherein:

said shields do not have any electrical connection other than to said sources and drains.

21. A non-volatile memory system, comprising:

a set of non-volatile storage elements arranged on a substrate, each non-volatile storage element comprising a floating gate;

a shield positioned between first and second floating gates which are associated with first and second adjacent word lines, respectively, the shield comprising an epitaxial portion on the substrate between the first and second floating gates, the epitaxial portion extending to a height which is at least between top and bottom portions of the first and second floating gates; and

insulating material covering a top side of each epitaxial portion, the top side of each epitaxial portion faces away from the substrate.

22. A non-volatile memory system according to claim 21, wherein:

the epitaxial portion is on a source/drain region of the substrate.

23. A non-volatile memory system according to claim 22, wherein:

the epitaxial portion is electrically connected to the source/drain region, but does not have any other electrical connection.

24. A non-volatile memory system according to claim 21, further comprising:

insulating material covering said epitaxial portion fully on opposing sides and fully on the top side of said epitaxial portion.

25. A non-volatile memory system according to claim 21, wherein the non-volatile storage elements comprise a plurality of adjacent pairs of non-volatile storage elements arranged in series on the substrate, the non-volatile memory system further comprising:

a plurality of shields, each respective shield positioned between two adjacent non-volatile storage elements in the adjacent pairs of non-volatile storage elements, each respective shield comprising a respective epitaxial portion grown on the substrate.

26. A non-volatile memory system according to claim 25, wherein:

each respective shield is positioned on a respective shared source/drain region for each respective adjacent pair of non-volatile storage elements.

27. A non-volatile memory system according to claim 25, wherein:

the plurality of adjacent pairs of non-volatile storage elements are arranged in series in a NAND string.