Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods

• US 7,355,273 B2
• Filed: 04/20/2005
• Issued: 04/08/2008
• Est. Priority Date: 07/31/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Murphy, Tim E., Jackson, Timothy L.
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US11/110,431
• Publication Number:
  US 20050186705A1
• Time in Patent Office: 1,084 Days
• Field of Search: 257/685, 257/686, 257/777, 257/E25.006, 257/E25.013, 257/E25.018, 257/E25.021, 257/E25.027, 257/E23.085, 257/E21.614
• US Class Current: 257/686
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.

Claims

1. A stacked semiconductor device assembly comprising:

a substrate;

a first semiconductor die directly electrically connected to the substrate;

a second semiconductor die disposed over the first semiconductor die, the second semiconductor die having an active surface, a back surface, and at least one via therethrough extending from the active surface to the back surface thereof;

a conductive material filling the at least one via; and

at least one electrically conductive redistribution line on the back surface of the second semiconductor die in electrical communication with the electrically conductive material of the at least one via and extending to a location on the back surface remote therefrom.

2. The stacked semiconductor device assembly of claim 1, wherein the second semiconductor die comprises a wafer.

3. The stacked semiconductor device assembly of claim 1, wherein the second semiconductor die comprises multiple, unsingulated semiconductor dice.

4. The stacked semiconductor device assembly of claim 1, further comprising at least one trace disposed on the active surface of the second semiconductor die and electrically connected to the electrically conductive material filling the at least one via.

5. The stacked semiconductor device assembly of claim 4, wherein the at least one trace electrically connects active circuitry on the active surface of the second semiconductor die to the electrically conductive material filling the at least one via.

6. The stacked semiconductor device assembly of claim 1, wherein the second semiconductor die includes at least one inner sidewall having a dielectric layer thereover, the electrically conductive material residing within the dielectric layer.

7. The stacked semiconductor device assembly of claim 1, wherein the electrically conductive material within the at least one via includes at least one of a metal, an alloy, a conductive polymer, a conductor-filled polymer and a conductively-doped portion of a semiconductor material matrix of the semiconductor die.

8. The stacked semiconductor device assembly of claim 1, wherein electrically conductive material of the at least one redistribution line includes at least one of a metal, an alloy, a conductive polymer and a conductor-filled polymer.

9. The stacked semiconductor device assembly of claim 1, wherein the location on the back surface corresponds with a location of a conductive bump positioned on the first semiconductor die.

10. The stacked semiconductor device assembly of claim 1, wherein the at least one via comprises a plurality of vias, the at least one redistribution line on the back surface comprises a plurality of redistribution lines, each in electrical communication with the conductive material of a via of the plurality, and wherein the locations on the back surface remote therefrom form, in combination, a pattern corresponding to a pattern of interconnects of another substrate to be superimposed thereto.

11. The stacked semiconductor device assembly of claim 10, further including electrically conductive bumps disposed over the electrically conductive redistribution lines on the locations on the back surface remote therefrom and projecting transversely from the back surface.

12. The stacked semiconductor device assembly of claim 11, wherein the electrically conductive bumps include at least one of a metal, an alloy, a conductive polymer and a conductor-filled polymer.

13. The stacked semiconductor device assembly of claim 12, wherein the electrically conductive bumps comprise solder.

14. The stacked semiconductor device assembly of claim 1, wherein the electrically conductive material of the at least one via is in direct electrical connection with integrated circuitry formed on the active surface.

15. The stacked semiconductor device assembly of claim 14, wherein the at least one via includes a bond pad formed thereover on the active surface.

16. The stacked semiconductor device assembly of claim 1, wherein the location on the back surface remote therefrom comprises a location configured to electrically connect to a wire bond.

17. The stacked semiconductor device assembly of claim 1, wherein the location on the back surface remote therefrom comprises a location of an interconnect of another substrate to be superimposed thereto.

18. The stacked semiconductor device assembly of claim 1, wherein a first surface of the substrate is electrically connected to at least one electrically conductive trace on the active surface of the first semiconductor die by way of an electrically conductive bump extending transversely therebetween.

19. The stacked semiconductor device assembly of claim 1, wherein the at least one redistribution line on the back surface of the second semiconductor die is electrically connected to the active surface of the first semiconductor die with an electrically conductive bump extending transversely therebetween.

20. The stacked semiconductor device assembly of claim 19, wherein the active surface of the second semiconductor die includes at least one wire bond extending therefrom to the first surface of the substrate.

21. The stacked semiconductor device assembly of claim 20, further comprising an encapsulation material formed at least over the at least one wire bond.

22. The stacked semiconductor device assembly of claim 1, wherein the active surface of the second semiconductor die is electrically connected to the active surface of the first semiconductor die with electrically conductive bumps extending transversely therebetween.

23. The stacked semiconductor device assembly of claim 1, further comprising a third semiconductor die having an active surface and a back surface, the third semiconductor die electrically connected to the second semiconductor die.

24. The stacked semiconductor device assembly of claim 23, wherein the third semiconductor die comprises:

at least one via extending from the active surface to the back surface thereof;

a conductive material disposed in the at least one via of the third semiconductor die and substantially extending a length thereof from the active surface to the back surface thereof; and

at least one redistribution line in electrical communication with the conductive material in the at least one via of the third semiconductor die and extending to a predetermined location on the back surface thereof.

25. The stacked semiconductor device assembly of claim 24, wherein the at least one redistribution line on the back surface of the third semiconductor die is electrically connected to the active surface of the second semiconductor die at the predetermined location of the at least one redistribution line of the third semiconductor die with an electrically conductive bump extending transversely therebetween.

26. The stacked semiconductor device assembly of claim 25, wherein the active surface of the third semiconductor die includes at least one wire bond extending therefrom to the first surface of the substrate.

27. The stacked semiconductor device assembly of claim 26, further comprising an encapsulation material formed at least over the at least one wire bond.

28. The stacked semiconductor device assembly of claim 23, wherein the active surface of the third semiconductor die is electrically connected to the active surface of the second semiconductor die with electrically conductive bumps extending transversely therebetween.

29. The stacked semiconductor device assembly of claim 1, wherein the back surface of the second semiconductor die comprises at least one electrical component positioned thereon.

30. The stacked semiconductor device assembly of claim 29, wherein the at least one electrical component comprises at least one of a capacitor, an inductor, a resistor, a fuse and a controller.

31. The stacked semiconductor device assembly of claim 29, wherein the at least one electrical component is electrically connected to the at least one redistribution line.