Single and composite binary and multi-valued logic functions from gates and inverters

• US 7,355,444 B2
• Filed: 03/15/2007
• Issued: 04/08/2008
• Est. Priority Date: 02/25/2004
• Status: Expired due to Fees

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Primary Examiner(s): LE, DON P
• Application Number:
  US11/686,542
• Publication Number:
  US 20070152710A1
• Time in Patent Office: 390 Days
• Field of Search: 326/37, 326/38, 326/59, 326/60, 326/104, 326/113
• US Class Current: 326/59
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.

Claims

1. A device implementing an n-valued logic function with n>

2, comprising;

an n-valued switch having an input and an output and a control input, wherein;

the input is enabled to receive a signal having one of n states;

the input is connected to the output whenever the control input is in a first of n-states; and

the input is isolated from the output whenever the control input is not in a first of n-states; and

an n-valued inverter.

2. The device as claimed in claim 1, wherein the n-valued inverter is reversible.

3. A method for implementing an n-valued logic function with n>

2, having an n by n truth table with n rows and n columns comprising;

implementing a row of the n by n truth table by an n-valued inverter; and

enabling the n-valued inverter by an n-valued switch having a control input.

4. The method as claimed in claim 3, wherein:

the n-valued switch further having an input and an output, wherein;

the input is enabled to receive a signal having one of n states;

the input is connected to the output whenever the control input is in a first of n-states; and

the input is isolated from the output whenever the control input is not in a first of n-states.

5. The method as claimed in claim 3, wherein the n-valued inverter implements

a column instead of a row of the n by n truth table.

6. A device implementing an n-valued logic function with n>

2 having 2 inputs and 1 output which is determined by a truth table, comprising;

an n-valued switch including an input, a control input and an output, the input enabled to receive a signal representing one of n logic states, the control input enabled to receive a signal representing one of n logic states and the output enabled to provide a signal representing one of n logic states, wherein;

the output of the n-valued logic switch provides a signal representing the one of n logic states represented by the signal received at the input of the n-valued switch whenever the control input receives a signal representing a first of n logic states; and

the output of the n-valued logic switch provides a signal that corresponds with an absence of signal at the input, whenever the control input receives a signal not representing a first of n logic states.

7. The device as claimed in claim 6, further comprising an n-valued inverter with an input and an output, the output of the inverter being connected to the input of the n-valued switch.

8. The device as claimed in claim 7, wherein the inverter represents a column or a row of the truth table.

9. The device as claimed in claim 6, wherein absence of signal represents one of n logic states.