Method for programming non-volatile memory with reduced program disturb using modified pass voltages

• US 7,355,889 B2
• Filed: 12/19/2005
• Issued: 04/08/2008
• Est. Priority Date: 12/19/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Hemink, Gerrit Jan, Oowada, Ken
• Primary Examiner(s): Nguyen; Tuan T.
• Assistant Examiner(s): Yang; Han
• Application Number:
  US11/313,023
• Publication Number:
  US 20070171719A1
• Time in Patent Office: 841 Days
• Field of Search: 365/185.17, 365/185.27, 365/185.11, 365/185.18
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.

Claims

1. A method for programming non-volatile storage, comprising:

programming a selected non-volatile storage element in a set of non-volatile storage elements by applying a programming voltage on a selected word line;

during the programming, applying a first voltage to at least a first word line which is associated with a previously programmed non-volatile storage element in the set to boost a potential of a first associated channel region, and applying a second voltage to at least a second word line which is associated with an unprogrammed and/or partly programmed non-volatile storage element in the set to boost a potential of a second associated channel region, the first voltage being greater than the second voltage; and

during the programming, forming an isolation region between the first and second associated channel regions by applying third through fifth voltages to third through fifth word lines, respectively, that are between the selected word line and the at least a first word line, the fourth word line being between the third and fifth word lines, the third through fifth voltages being less than the first voltage, and the fourth voltage being less than the third and fifth voltages.

2. The method of claim 1, wherein:

the first voltage is greater than the second voltage by approximately two to three volts.

3. The method of claim 1, wherein:

the first associated channel region is a source side channel region, and the second associated channel region is a drain side channel region.

4. The method of claim 1, wherein:

the set is programmed starting from a source side of the set and ending at a drain side of the set, the at least a first word line comprises a source side word line and the at least a second word line comprises drain side word line.

5. The method of claim 1, wherein:

the fourth voltage is approximately 0-1 Volts.

6. The method of claim 1, wherein:

the third and fifth voltages are approximately equal.

7. The method of claim 1, wherein:

the third voltage is greater than the fourth voltage.

8. The method of claim 1, wherein:

during the programming, the first voltage is applied to a first plurality of adjacent word lines which are associated with previously programmed non-volatile storage elements in the set, and the second voltage is applied to a second plurality of adjacent word lines which are associated with unprogrammed and/or partly programmed non-volatile storage elements in the set.

9. The method of claim 1, wherein:

the non-volatile storage elements comprise multi-level storage elements.

10. The method of claim 1, wherein:

the set of non-volatile storage elements comprises a NAND string.

11. A method for programming non-volatile storage, comprising:

programming a selected non-volatile storage element in a set of non-volatile storage elements by applying a programming voltage on a selected word line; and

during the programming, applying a first voltage to at least a first word line associated with a previously programmed non-volatile storage element in the set to boost a potential of a first associated channel region, applying a second voltage to at least a second word line associated with an unprogrammed and/or partly programmed non-volatile storage element in the set to boost a potential of a second associated channel region, and applying third through seventh voltages to third through seventh adjacent word lines, respectively, which are associated with previously programmed non-volatile storage elements in the set, and which are between the at least a first word line and the selected word line, to form an isolation region between the first and second associated channel regions, the fifth word line is between the fourth and sixth word lines, the fourth and sixth word lines are between the third and seventh word lines, the third through seventh voltages are less than the first voltage, the fifth voltage is less than the fourth and sixth voltages, and the sixth voltage is less than the seventh voltage.

12. The method of claim 11, wherein:

the third voltage is greater than the fourth voltage.

13. The method of claim 12, wherein:

the third and seventh voltages are greater than the fourth and sixth voltages.

14. The method of claim 12, wherein:

the fourth and sixth voltages are approximately equal; and

the third and seventh voltages are approximately equal.

15. The method of claim 11, wherein:

the first voltage is greater than the second voltage by an amount which is sufficient to reduce leakage of charge from the second associated channel region to the first associated channel region.

16. The method of claim 11, wherein:

the first voltage is greater than the second voltage by approximately two to three volts.

17. The method of claim 11, wherein:

the at least a first word line and the third through seventh word lines are on a source side of the selected word line and the at least a second word line is on a drain side of the selected word line.

18. The method of claim 11, wherein:

the set is programmed starting from a source side of the set and ending at a drain side of the set.

19. The method of claim 11, wherein:

the first associated channel region is a source side channel region, and the second associated channel region is a drain side channel region.

20. The method of claim 11, wherein:

the non-volatile storage elements comprise multi-level storage elements.

21. The method of claim 11, wherein:

the set of non-volatile storage elements comprises a NAND string.