Memory circuit with supply voltage flexibility and supply voltage adapted performance
First Claim
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1. A memory circuit comprising:
- a plurality of memory cells organized in rows and columns;
memory access circuitry controlled by at least one control signal; and
control circuitry for generating the at least one control signal comprising;
delay circuitry which delays a switching of the at least one control signal with a respective delay time being adjustable in view of an applied supply voltage, whereinthe memory access circuitry supports a memory read access mode and a memory write access mode; and
the delay time is independently selectable for the memory read access mode and for the memory write access mode.
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Abstract
The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained in the memory circuit, with the control means comprising a delay means. The delay means delays a switching of the at least one control signal. The delay time is adjustable in view of the applied supply voltage.
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Citations
6 Claims
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1. A memory circuit comprising:
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a plurality of memory cells organized in rows and columns; memory access circuitry controlled by at least one control signal; and control circuitry for generating the at least one control signal comprising; delay circuitry which delays a switching of the at least one control signal with a respective delay time being adjustable in view of an applied supply voltage, wherein the memory access circuitry supports a memory read access mode and a memory write access mode; and the delay time is independently selectable for the memory read access mode and for the memory write access mode. - View Dependent Claims (2, 3)
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4. A memory circuit comprising:
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a plurality of memory cells organized in rows and columns; a plurality of bit lines each coupled to a column of the plurality of memory cells; memory access circuitry controlled by at least one control signal; and control circuitry for generating the at least one control signal comprising; delay circuitry which delays a switching of the at least one control signal with a respective delay time being adjustable in view of an applied supply voltage, wherein the delay circuitry comprises; a dummy bit line coupled to dummy memory cells, wherein a signal transmission behavior of the dummy bit line is characteristic of a signal transmission behavior of the bit lines, and wherein the at least one control signal is generated using the signal on the dummy bit line; and a driver unit driving the dummy bit line, wherein the driver discharges the dummy bit line, wherein a driving capability of the driver unit is independently selectable for at least two different supply voltage operating modes of the memory circuit, wherein the supply voltage operating modes include a high supply voltage mode and a low supply voltage mode, and wherein the driving capability for the high supply voltage mode is higher than the driving capability for the low supply voltage mode. - View Dependent Claims (5, 6)
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Specification