Adaptive radio transceiver with floating MOSFET capacitors

• US 7,356,310 B2
• Filed: 04/18/2005
• Issued: 04/08/2008
• Est. Priority Date: 10/21/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Maryam, Khorram, Shahla, Rofougaran, Ahmadreza
• Primary Examiner(s): Nguyen; Tony T.
• Assistant Examiner(s): Nguyen; Thuan T.
• Application Number:
  US11/108,460
• Publication Number:
  US 20050186925A1
• Time in Patent Office: 1,086 Days
• Field of Search: 455/66.1, 455/76, 455/86, 455/323, 455/73, 455/31.3, 455/75, 455/78, 327/427, 327/434, 327/437, 361/270, 361/281, 375/219, 375/147, 375/150
• US Class Current: 455/66.1
• CPC Class Codes: H03B 21/01 by beating unmodulated signals of different frequencies
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45386 the AAC comprising one or more coils in the source circuit
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03H 11/126 using a single operational amplifier H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 11/344 : Duplexers
• CPC Class Codes: H03H 2011/0494 : Complex filters
• CPC Class Codes: H03H 21/0001 : Analogue adaptive filters
• CPC Class Codes: H03H 21/0012 : Digital adaptive filters
• CPC Class Codes: H03H 2210/025 : Capacitor
• CPC Class Codes: H03H 2210/036 : Stepwise
• CPC Class Codes: H03H 7/42 : Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 17/104 : of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04B 17/14 : of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/19 : Self-testing arrangements

Abstract

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. A method for providing a capacitance device in an integrated circuit, comprising:

providing an input of the capacitance device, the input of the capacitance device comprising a first source node and a first drain node of a first transistor;

operatively coupling the first source node with the first drain node;

operatively coupling a first gate node of the first transistor to a second gate node of a second transistor;

providing an output of the capacitance device, the output of the capacitance device comprising a second source node and a second drain node of the second transistor; and

operatively coupling the second source node to the second drain node.

2. The method according to claim 1, comprising:

operatively coupling a resistor to the first gate node and the second gate node.

3. The method according to claim 1, wherein the first transistor is in series with the second transistor.

4. The method according to claim 1, comprising:

operatively coupling a bias source to the first gate node and the second gate node.

5. The method according to claim 1, comprising:

inputting a signal at the input of the capacitance device.

6. The method according to claim 5, wherein the signal carries substantially no DC information.

7. The method according to claim 1, comprising:

outputting a signal at the output of the capacitance device.

8. The method according to claim 7, wherein the signal carries substantially no DC information.

9. The method according to claim 1, wherein the first transistor and the second transistor use CMOS technology.

10. The method according to claim 1, wherein the capacitance device comprises a floating capacitance device.

11. A method for providing a capacitance device, comprising:

(a) operatively coupling a first transistor to a second transistor in series;

(b) inputting an input signal to an input of the first transistor, the input of the first transistor comprising a first node and a second node of the first transistor;

(c) operatively coupling the first node and the second node of the first transistor;

(d) operatively coupling a third node and a fourth node of the second transistor; and

(e) outputting an output signal from an output of the second transistor, the output of the second transistor comprising the third node and the fourth node.

12. The method according to claim 11, wherein (a) comprises operatively coupling a fifth node of the first transistor to a sixth node of the second transistor.

13. The method according to claim 12,

wherein the fifth node comprises a gate node of the first transistor, and

wherein the sixth node comprises a gate node of the second transistor.

14. The method according to claim 11, comprising:

integrating the capacitance device into an integrated circuit.

15. The method according to claim 11,

wherein the first node of the first transistor comprises a source node of the first transistor,

wherein the second node of the first transistor comprises a drain node of the first transistor,

wherein the third node of the second transistor comprises a source node of the second transistor, and

wherein the fourth node of the second transistor comprises a drain node of the second transistor.

16. The method according to claim 11, comprising;

(f) biasing the first transistor and the second transistor via the fifth node of the first transistor and the sixth node of the second transistor.

17. The method according to claim 16, wherein (f) comprises biasing the first transistor and the second transistor via a shared resistor.

18. The method according to claim 11, wherein the capacitance device provides a floating capacitance.

19. The method according to claim 11,

wherein the input signal carries substantially no DC information, and

wherein the output signal carries substantially no DC information.

20. The method according to claim 11, wherein the first transistor or the second transistor uses MOS technology.