Apparatus and method for removing DC offset in a frequency direct-conversion device

• US 7,356,320 B2
• Filed: 12/20/2004
• Issued: 04/08/2008
• Est. Priority Date: 12/18/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Bae, Sang-Min, Ha, Ji-Won, Lim, Jong-Han, Yeo, Soo-Bok, Shin, Yong-Won
• Primary Examiner(s): Le; Thanh Cong
• Application Number:
  US11/015,471
• Publication Number:
  US 20050136874A1
• Time in Patent Office: 1,205 Days
• Field of Search: None
• US Class Current: 455/234.1
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

An apparatus for removing a DC offset during frequency direct conversion in a reception device of a wireless communication system. In the apparatus, an adder receives a digital baseband signal comprising a DC component, receives an estimated DC offset value, and calculates a difference between the digital baseband signal with the DC component and the estimated DC offset value. A DC offset calculator receives gain mode information of an analog element of the reception device, and calculates the estimated DC offset value according to the gain mode.

Claims

1. An apparatus for removing a DC offset during frequency direct conversion in a reception device of a wireless communication system, the apparatus comprising:

a first adder for receiving a DC corrupted digital baseband signal, receiving an estimated DC offset value, and calculating a difference between the DC corrupted digital baseband signal and the estimated DC offset value; and

a DC offset calculator for receiving gain mode information of an analog element of the reception device, and calculating the estimated DC offset value according to the gain mode.

2. The apparatus of claim 1, further comprising a DC offset decider for compensating for a loop gain and a filter gain from the estimated DC offset value.

3. The apparatus of claim 1, further comprising an accumulator for receiving an output of the first adder, accumulating as many input symbols as a predetermined value for removal of a channel noise and an element noise, and outputting the accumulated symbols to the DC offset calculator.

4. The apparatus of claim 3, further comprising a second adder connected between the accumulator and the DC offset calculator, for compensating for asymmetricity of the accumulated symbols.

5. The apparatus of claim 4, wherein the second adder adds M/2 to an output of the accumulator, wherein M denotes the number of accumulated symbols.

6. The apparatus of claim 4, further comprising a switch connected between the second adder and the DC offset calculator, for inputting the accumulated symbols to the DC offset calculator every M symbols, wherein M denotes the number of accumulated symbols.

7. The apparatus of claim 1, further comprising:

a digital filter for low-pass-filtering an output signal of the first adder; and

a demodulator for demodulating an output signal of the digital filter.

8. The apparatus of claim 1, wherein the DC offset calculator comprises:

a multiplier for multiplying an input signal of the DC offset calculator by a predetermined constant gain;

a third adder for calculating a difference between an output of the multiplier and a DC offset value estimated according to the gain mode;

a delay for delaying an output of the third adder for a predetermined time; and

an accumulation register for selecting a gain mode depending on the gain mode information of the analog element, storing an output of the delay according to the selected gain mode, and outputting one of the stored values to the third adder.

9. The apparatus of claim 8, wherein the constant gain has different values for initial driving and normal operation, respectively.

10. The apparatus of claim 9, wherein the constant gain for initial driving is larger than the constant gain for normal operation.

11. The apparatus of claim 8, wherein the accumulation register includes register elements for storing different values according to gain modes.

12. The apparatus of claim 1, further comprising a digital DC offset decider, which is connected between the DC offset calculator and the first adder, for compensating for the calculated DC offset value.

13. A method for removing a DC offset during frequency direct conversion in a reception device of a wireless communication system, the method comprising the steps of:

selecting a gain mode depending on gain mode information of an analog element, and estimating a DC offset value according to the selected gain mode;

compensating for a loop gain and a filter gain from the estimated DC offset value; and

subtracting the gain compensated-DC offset value from a DC corrupted digital baseband signal.

14. The method of claim 13, further comprising the steps of:

low-pass-filtering the signal determined by subtracting the gain compensated-DC offset value from the DC corrupted digital baseband signal and

demodulating the low-pass-filtered signal.

15. The method of claim 13, further comprising the steps of:

accumulating as many symbols from which the estimated DC offset value is subtracted as a predetermined number; and

compensating for asymmetricity of quantization from the accumulated signal.

16. The method of claim 13, wherein the step of estimating a DC offset value comprises the steps of:

multiplying an input signal by a predetermined constant gain;

adding a DC offset value determined according to a gain mode, to the multiplication result; and

delaying the addition result for a predetermined time, and storing the delayed value.