Decryption semiconductor circuit

• US 7,356,708 B2
• Filed: 02/03/2004
• Issued: 04/08/2008
• Est. Priority Date: 02/04/2003
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Dellow, Andrew
• Primary Examiner(s): NGUYEN, MINH DIEU T
• Application Number:
  US10/773,089
• Publication Number:
  US 20040223618A1
• Time in Patent Office: 1,526 Days
• Field of Search: 380/277, 713/189, 713/153, 364/200, 326/8, 257/7, 725/31, 725/87, 725/104, 709238-240
• US Class Current: 713/189
• CPC Class Codes: H04L 2209/601 Broadcast encryption
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0827 involving distinctive intermediate devices or communication paths network architectures or network communication protocols using different networks H04L63/18

Abstract

A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and to selectively provide the encrypted or decrypted data to at least one of the data destinations; an instruction interpreter arranged to receive an instruction signal and to generate an output to control the plurality of selectable pathways to select from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides data. The instruction interpreter configured such that the instruction signal defines a data pathway that operates in accordance with a rule that limits the data pathway configurations which are selectable.

Claims

1. A semiconductor integrated circuit, comprising:

a plurality of selectable pathways inter-connected between a plurality of data sources and data destinations;

a cryptographic circuit connected to the selectable pathways and arranged to selectively receive data at an input from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and selectively provide the encrypted or decrypted data to at least one of the data destinations via an output;

an instruction circuit arranged to receive on a first input an instruction signal and to generate therefrom an output to control the plurality of selectable pathways to select a data pathway configuration of the circuit, thereby selecting from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides the data;

wherein the instruction circuit is configurable by a limiting rule signal, received at a second input, to operate in accordance with the rule signal that limits the data pathway configurations that are selectable by the instruction signal, thereby limiting flow of data between the data sources and data destinations.

2. The semiconductor integrated circuit of claim 1 wherein the a rule signal defines those data pathway configurations that are unselectable.

3. The semiconductor integrated circuit of claim 2 wherein the rule signal is chosen from a plurality of rule signals according to a mode of operation of the system.

4. The semiconductor integrated circuit of claim 3 wherein the plurality of rule signals are generated by a rule selector, and wherein the rule selector comprises a plurality of anti-fuses allowing one of a plurality of selectable configurations to be chosen.

5. The semiconductor integrated circuit of claim 4 wherein each of the anti-fuses can be configured once only.

6. The semiconductor integrated circuit of claim 1 wherein the instruction signal is generated by a CPU.

7. The semiconductor integrated circuit of claim 6 wherein the CPU is arranged to generate the instruction signal comprising an instruction portion and a data portion.

8. The semiconductor integrated circuit of claim 1 wherein the instruction signal and rule signal are 32-bit data fields.

9. The semiconductor integrated circuit of claim 1 wherein the plurality of data sources and destinations includes at least one memory for storing encryption or decryption keys.

10. The semiconductor integrated circuit of claim 9 wherein one of the key memories stores at least one key generated by a software algorithm.

11. The semiconductor integrated circuit of claim 9 wherein one of the key memories stores at least one service key for decrypting control words.

12. The semiconductor integrated circuit of claim 9 wherein one of the key memories stores a secret key for decrypting service keys.

13. The semiconductor integrated circuit of claim 1 wherein the key is selected from a plurality of keys in dependence on the instruction signal.

14. The semiconductor integrated circuit of claim 13 wherein the key is selected from one of a plurality of key stores and provided to a key input of the cryptographic circuit in dependence on the instruction signal.

15. The semiconductor integrated circuit of claim 13 wherein the cryptographic circuit has a key input, and the key provided to the key input is selected in accordance with the selected pathway.

16. The semiconductor integrated circuit of claim 15 wherein the plurality of selectable pathways are configurable such that when the data from the data source is a service key, the cryptographic circuit receives a secret key at the key input.

17. The semiconductor integrated circuit of claim 15 wherein the plurality of selectable pathways are configurable such that when the data source is a memory and the data destination is a memory, the cryptographic circuit receives a software written key at the key input.

18. The semiconductor integrated circuit of claim 15 wherein the plurality of selectable pathways are configurable such that when the data source is a plurality of control words, the cryptographic circuit receives a service key at the key input.

19. The semiconductor integrated circuit of claim 15 wherein the plurality of selectable pathways are configurable such that when the data source is broadcast data, the cryptographic circuit receives a software written key at the key input.

20. The semiconductor integrated circuit of claim 1 wherein the circuit is arranged to descramble television broadcast signals using a series of control words.

21. The semiconductor integrated circuit of claim 1 wherein the circuit is arranged to decrypt encrypted control words using a service key.

22. The semiconductor integrated circuit of claim 1 wherein the circuit is arranged to decrypt encrypted service keys using a secret key.

23. The semiconductor integrated circuit of claim 1 wherein the circuit is arranged to perform memory-to-memory transfers.

24. The semiconductor integrated circuit of claim 1 wherein the plurality of data sources and destinations includes at least one of a hard disc, ROM, RAM, data in port and data out port.

25. The semiconductor integrated circuit of claim 1 wherein the cryptographic circuit is an AES circuit.

26. The semiconductor integrated circuit of claim 1 wherein the plurality of selectable pathways are selected by at least one multiplexer or switch.

27. The semiconductor integrated circuit of claim 1 wherein the instruction circuit comprises a plurality of combinatorial components arranged such that the output is generated as a function of the instruction signal.

28. The semiconductor integrated circuit of claim 1 wherein an encryption system is a subscriber-based pay-television system.

29. The semiconductor integrated circuit of claim 1 wherein an encryption system is a monolithic integrated circuit.