Method and apparatus for error code correction

• US 7,356,753 B2
• Filed: 10/08/2004
• Issued: 04/08/2008
• Est. Priority Date: 10/08/2003
• Status: Expired due to Fees

• Current Assignee: Tian Holdings LLC (Intellectual Ventures LLC)
• Original Assignee: Tian Holdings LLC (Intellectual Ventures LLC)
• Inventors: Chen, Jonathan
• Primary Examiner(s): CHASE, SHELLY A
• Application Number:
  US10/961,933
• Publication Number:
  US 20050081132A1
• Time in Patent Office: 1,278 Days
• Field of Search: 714755-756
• US Class Current: 714/755
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 2020/183 wherein at least one additional attempt is made to read or write the data when a first attempt is unsuccessful
• CPC Class Codes: G11B 2020/1836 using a Reed Solomon [RS] code

Abstract

A method and apparatus for ECC (error code correction) adopts a first directional first decoding, a first directional second decoding with a greater error tolerant ability than the first directional first decoding, a second directional first decoding, and a second directional second decoding with a greater error tolerant ability than the second directional first decoding. The ECC method includes steps of: read to be decoded; if there exists at least one solution cannot be efficiently solved after continuous executing the first directional first decoding and the second directional second decoding, execute the decoding action according to a predetermined flow control rule; if there exists no correction performed during the ECC decoding and switch to the other directional decoding, the un-modified value is added by one; and if the un-modified value reached a maximum un-modified value, an ECC failure is confirmed and then stop the ECC decoding.

Claims

1. An error correction method for detecting and correcting an error in an ECC (error correction code) block read from a storage medium, said ECC block including a PI (parity of inner-code) block and a PO (parity outer-code) block, the method comprising:

executing a first directional ECC decoding and a second directional ECC decoding iteratively if a retry count of one of said first directional ECC decoding and said second directional ECC decoding being less than a first threshold count, otherwise regarding as ECC failure (skipping out of the ECC method); and

executing the first directional ECC decoding and the second directional ECC decoding iteratively if an un-modified count of one of said first ECC decoding and said second ECC decoding being less than a second threshold count, otherwise regarding as ECC failure (skipping out of the ECC method).

2. The method as claimed in claim 1, wherein the first directional ECC decoding comprises a PI decoding and the second directional ECC decoding comprises a PO decoding.

3. The method as claimed in claim 2, wherein the first directional ECC decoding further comprises a random error process.

4. The method as claimed in claim 2, wherein the second directional ECC decoding further comprises a random error process.

5. The method as claimed in claim 2, wherein the error correction method further comprises a step of executing an auxiliary PO decoding with marking erasure process followed after the PO decoding if a decode error or an un-correctable error read from the storage medium is detected.

6. The method as claimed in claim 2, wherein the error correction method further comprises a step of executing an auxiliary PI decoding with a marking erasure process followed after the PI decoding if a decode error or an un-correctable error is read from the storage medium is detected.

7. The method as claimed in claim 2, wherein the PI decoding can be one of a Reed-Solomon Product Code (RSPC) decoding and a Cross Interleave Reed-Solomon Code (CIRS) decoding.

8. The method as claimed in claim 2, wherein the PO decoding can be one of a Reed-Solomon Product Code (RSPC) decoding and a Cross Interleave Reed-Solomon Code (CIRS) decoding.

9. An error correction apparatus for detecting and correcting an error in an ECC (error correction code) block read from a storage medium, said ECC block including a PI (parity of inner-code) block and a PO (parity outer-code) block, the apparatus comprising:

means for executing a first directional ECC decoding and a second directional ECC decoding iteratively if a retry count of one of said first directional ECC decoding and said second directional ECC decoding being less than a first threshold count, otherwise regarding as ECC failure (skipping out of the ECC method); and

means for executing the first directional ECC decoding and the second directional ECC decoding iteratively if an un-modified count of one of said first ECC decoding and said second ECC decoding being less than a second threshold count, otherwise regarding as ECC failure (skipping out of the ECC method).

10. The apparatus as claimed in claim 9, wherein the means for executing first directional ECC decoding and the second directional ECC decoding comprises a PI decoder and a PO decoder.

11. The apparatus as claimed in claim 10, wherein the PI decoder further comprises a circuit for executing a random error process.

12. The apparatus as claimed in claim 10, wherein the PO decoding further comprises a circuit for executing a random error process.

13. The apparatus as claimed in claim 10, wherein the error correction apparatus further comprises a circuit for executing an auxiliary PO decoding with marking erasure process followed after the PO decoding if a decode error or an un-correctable error read from the storage medium is detected.

14. The apparatus as claimed in claim 10, wherein the error correction apparatus further comprises a circuit for executing an auxiliary PI decoding with a marking erasure process followed after the PI decoding if a decode error or an un-correctable error is read from the storage medium is detected.

15. The apparatus as claimed in claim 10, wherein the PI decoder can be one of a Reed-Solomon Product Code (RSPC) decoder and a Cross Interleave Reed-Solomon Code (CIRS) decoder.

16. The apparatus as claimed in claim 10, wherein the PO decoder can be one of a Reed-Solomon Product Code (RSPC) decoder and a Cross Interleave Reed-Solomon Code (CIRS) decoder.